OpenCores
URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [rtos/] [ecos-2.0/] [packages/] [devs/] [eth/] [powerpc/] [mbx/] [v2_0/] [include/] [mbx_eth.inl] - Blame information for rev 355

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 27 unneback
#ifndef CYGONCE_DEVS_MBX_ETH_INL
2
#define CYGONCE_DEVS_MBX_ETH_INL
3
//==========================================================================
4
//
5
//      mbx_eth.inl
6
//
7
//      Hardware specifics for Motorola MBX ethernet support
8
//
9
//==========================================================================
10
//####ECOSGPLCOPYRIGHTBEGIN####
11
// -------------------------------------------
12
// This file is part of eCos, the Embedded Configurable Operating System.
13
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
14
// Copyright (C) 2002 Gary Thomas
15
//
16
// eCos is free software; you can redistribute it and/or modify it under
17
// the terms of the GNU General Public License as published by the Free
18
// Software Foundation; either version 2 or (at your option) any later version.
19
//
20
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
21
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
22
// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
23
// for more details.
24
//
25
// You should have received a copy of the GNU General Public License along
26
// with eCos; if not, write to the Free Software Foundation, Inc.,
27
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
28
//
29
// As a special exception, if other files instantiate templates or use macros
30
// or inline functions from this file, or you compile this file and link it
31
// with other works to produce a work based on this file, this file does not
32
// by itself cause the resulting work to be covered by the GNU General Public
33
// License. However the source code for this file must still be made available
34
// in accordance with section (3) of the GNU General Public License.
35
//
36
// This exception does not invalidate any other reasons why a work based on
37
// this file might be covered by the GNU General Public License.
38
//
39
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
40
// at http://sources.redhat.com/ecos/ecos-license/
41
// -------------------------------------------
42
//####ECOSGPLCOPYRIGHTEND####
43
//==========================================================================
44
//#####DESCRIPTIONBEGIN####
45
//
46
// Author(s):    gthomas
47
// Contributors: gthomas
48
// Date:         2002-11-19
49
// Purpose:
50
// Description:
51
//
52
//####DESCRIPTIONEND####
53
//
54
//==========================================================================
55
 
56
#define _get_led()
57
#define _set_led(v)
58
 
59
#define LED_TxACTIVE  7
60
#define LED_RxACTIVE  6
61
#define LED_IntACTIVE 5
62
 
63
#if 0
64
// Fetch ESA from on-board EEPROM
65
extern int _mbx_fetch_VPD(int, void *, int);
66
#define QUICC_ETH_FETCH_ESA(_ok_)                              \
67
     _ok_ = _mbx_fetch_VPD(VPD_ETHERNET_ADDRESS, enaddr, sizeof(enaddr));
68
#endif
69
 
70
// Reset/enable any external hardware
71
#define QUICC_ETH_ENABLE()                                     \
72
    *MBX_CTL1 = MBX_CTL1_ETEN | MBX_CTL1_TPEN;  /* Enable ethernet, TP mode */
73
 
74
 
75
// Port layout - uses SCC1
76
#define QUICC_ETH_PA_RXD            0x0001  // Rx Data on Port A
77
#define QUICC_ETH_PA_TXD            0x0002  // Tx Data on Port A
78
#define QUICC_ETH_PA_Tx_CLOCK       0x0200  // Tx Clock = CLK2
79
#define QUICC_ETH_PA_Rx_CLOCK       0x0800  // Rx Clock = CLK4
80
#define QUICC_ETH_PC_Tx_ENABLE      0x0001  // Tx Enable (TENA)
81
#define QUICC_ETH_PC_COLLISION      0x0010  // Collision detect
82
#define QUICC_ETH_PC_Rx_ENABLE      0x0020  // Rx Enable (RENA)
83
#define QUICC_ETH_SICR_MASK         0x00FF  // SI Clock Route - important bits
84
#define QUICC_ETH_SICR_ENET  (7<<3)|(5<<0)  //   Rx=CLK4, Tx=CLK2
85
#define QUICC_ETH_SICR_ENABLE       0x0040  // Enable SCC1 to use NMSI
86
#define QUICC_ETH_INT               CYGNUM_HAL_INTERRUPT_CPM_SCC1
87
#define QUICC_ETH_SCC               0       // SCC1
88
#define QUICC_CPM_SCCx              QUICC_CPM_SCC1
89
 
90
#define MBX_CTL1   (cyg_uint8 *)0xFA100000  // System control register
91
#define MBX_CTL1_ETEN                 0x80  // 1 = Enable ethernet tranceiver
92
#define MBX_CTL1_ELEN                 0x40  // 1 = Enable ethernet loopback
93
#define MBX_CTL1_EAEN                 0x20  // 1 = Auto select ethernet interface
94
#define MBX_CTL1_TPEN                 0x10  // 0 = AUI, 1 = TPI
95
#define MBX_CTL1_FDDIS                0x08  // 1 = Disable full duplex (if TP mode)
96
 
97
 
98
#endif  // CYGONCE_DEVS_MBX_ETH_INL
99
// ------------------------------------------------------------------------

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.