OpenCores
URL https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk

Subversion Repositories openrisc_2011-10-31

[/] [openrisc/] [trunk/] [rtos/] [ecos-2.0/] [packages/] [devs/] [flash/] [intel/] [28fxxx/] [v2_0/] [include/] [flash_28fxxx.inl] - Blame information for rev 174

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 27 unneback
#ifndef CYGONCE_DEVS_FLASH_INTEL_28FXXX_INL
2
#define CYGONCE_DEVS_FLASH_INTEL_28FXXX_INL
3
//==========================================================================
4
//
5
//      flash_28fxxx.inl
6
//
7
//      Intel 28Fxxx series flash driver
8
//
9
//==========================================================================
10
//####ECOSGPLCOPYRIGHTBEGIN####
11
// -------------------------------------------
12
// This file is part of eCos, the Embedded Configurable Operating System.
13
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
14
// Copyright (C) 2002 Gary Thomas
15
//
16
// eCos is free software; you can redistribute it and/or modify it under
17
// the terms of the GNU General Public License as published by the Free
18
// Software Foundation; either version 2 or (at your option) any later version.
19
//
20
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
21
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
22
// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
23
// for more details.
24
//
25
// You should have received a copy of the GNU General Public License along
26
// with eCos; if not, write to the Free Software Foundation, Inc.,
27
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
28
//
29
// As a special exception, if other files instantiate templates or use macros
30
// or inline functions from this file, or you compile this file and link it
31
// with other works to produce a work based on this file, this file does not
32
// by itself cause the resulting work to be covered by the GNU General Public
33
// License. However the source code for this file must still be made available
34
// in accordance with section (3) of the GNU General Public License.
35
//
36
// This exception does not invalidate any other reasons why a work based on
37
// this file might be covered by the GNU General Public License.
38
//
39
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
40
// at http://sources.redhat.com/ecos/ecos-license/
41
// -------------------------------------------
42
//####ECOSGPLCOPYRIGHTEND####
43
//==========================================================================
44
//#####DESCRIPTIONBEGIN####
45
//
46
// Author(s):    jskov
47
// Contributors: jskov
48
// Date:         2001-03-21
49
// Purpose:
50
// Description:
51
//
52
// Notes:        Device table could use unions of flags to save some space
53
//
54
//####DESCRIPTIONEND####
55
//
56
//==========================================================================
57
 
58
#include 
59
#include 
60
#include 
61
 
62
#include 
63
#include 
64
#include CYGHWR_MEMORY_LAYOUT_H
65
 
66
#include 
67
 
68
#define  _FLASH_PRIVATE_
69
#include 
70
 
71
#define nDEBUG
72
 
73
#ifdef DEBUG
74
typedef void (*call_t)(char* str, ...);
75
extern void diag_printf(char* str, ...);
76
call_t d_print = &diag_printf;
77
#endif
78
 
79
//----------------------------------------------------------------------------
80
// Common device details.
81
#define FLASH_Read_ID                   FLASHWORD( 0x90 )
82
#define FLASH_Reset                     FLASHWORD( 0xFF )
83
#define FLASH_Program                   FLASHWORD( 0x40 )
84
#define FLASH_Write_Buffer              FLASHWORD( 0xe8 )
85
#define FLASH_Block_Erase               FLASHWORD( 0x20 )
86
#define FLASH_Confirm                   FLASHWORD( 0xD0 )
87
#define FLASH_Resume                    FLASHWORD( 0xD0 )
88
 
89
#define FLASH_Set_Lock                  FLASHWORD( 0x60 )
90
#define FLASH_Set_Lock_Confirm          FLASHWORD( 0x01 )
91
#define FLASH_Clear_Lock                FLASHWORD( 0x60 )
92
#define FLASH_Clear_Lock_Confirm        FLASHWORD( 0xd0 )
93
 
94
#define FLASH_Read_Status               FLASHWORD( 0x70 )
95
#define FLASH_Clear_Status              FLASHWORD( 0x50 )
96
#define FLASH_Status_Ready              FLASHWORD( 0x80 )
97
 
98
// Status that we read back:
99
#define FLASH_ErrorMask                 FLASHWORD( 0x7E )
100
#define FLASH_ErrorProgram              FLASHWORD( 0x10 )
101
#define FLASH_ErrorErase                FLASHWORD( 0x20 )
102
#define FLASH_ErrorLock                 FLASHWORD( 0x30 )
103
#define FLASH_ErrorLowVoltage           FLASHWORD( 0x08 )
104
#define FLASH_ErrorLocked               FLASHWORD( 0x02 )
105
 
106
// Platform code must define the below
107
// #define CYGNUM_FLASH_INTERLEAVE      : Number of interleaved devices (in parallel)
108
// #define CYGNUM_FLASH_SERIES          : Number of devices in series
109
// #define CYGNUM_FLASH_WIDTH           : Width of devices on platform
110
// #define CYGNUM_FLASH_BASE            : Address of first device
111
 
112
#define CYGNUM_FLASH_BLANK              (1)
113
#define CYGNUM_FLASH_DEVICES            (CYGNUM_FLASH_INTERLEAVE*CYGNUM_FLASH_SERIES)
114
 
115
 
116
#ifndef FLASH_P2V
117
# define FLASH_P2V( _a_ ) ((volatile flash_data_t *)((CYG_ADDRWORD)(_a_)))
118
#endif
119
#ifndef CYGHWR_FLASH_28FXXX_PLF_INIT
120
# define CYGHWR_FLASH_28FXXX_PLF_INIT()
121
#endif
122
#ifndef CYGHWR_FLASH_WRITE_ENABLE
123
#define CYGHWR_FLASH_WRITE_ENABLE()
124
#endif
125
#ifndef CYGHWR_FLASH_WRITE_DISABLE
126
#define CYGHWR_FLASH_WRITE_DISABLE()
127
#endif
128
 
129
//----------------------------------------------------------------------------
130
// Now that device properties are defined, include magic for defining
131
// accessor type and constants.
132
#include 
133
 
134
//----------------------------------------------------------------------------
135
// Information about supported devices
136
typedef struct flash_dev_info {
137
    flash_data_t device_id;
138
    cyg_uint32   block_size;
139
    cyg_int32    block_count;
140
    cyg_uint32   base_mask;
141
    cyg_uint32   device_size;
142
    cyg_bool     locking;               // supports locking
143
    cyg_bool     buffered_w;            // supports buffered writes
144
    cyg_bool     bootblock;
145
    cyg_uint32   bootblocks[12];         // 0 is bootblock offset, 1-11 sub-sector sizes (or 0)
146
    cyg_bool     banked;
147
    cyg_uint32   banks[2];               // bank offets, highest to lowest (lowest should be 0)
148
                                         // (only one entry for now, increase to support devices
149
                                         // with more banks).
150
} flash_dev_info_t;
151
 
152
static const flash_dev_info_t* flash_dev_info;
153
static const flash_dev_info_t supported_devices[] = {
154
#include 
155
};
156
#define NUM_DEVICES (sizeof(supported_devices)/sizeof(flash_dev_info_t))
157
 
158
//----------------------------------------------------------------------------
159
// Functions that put the flash device into non-read mode must reside
160
// in RAM.
161
void flash_query(void* data) __attribute__ ((section (".2ram.flash_query")));
162
int  flash_erase_block(void* block, unsigned int size)
163
    __attribute__ ((section (".2ram.flash_erase_block")));
164
int  flash_program_buf(void* addr, void* data, int len,
165
                       unsigned long block_mask, int buffer_size)
166
    __attribute__ ((section (".2ram.flash_program_buf")));
167
int  flash_lock_block(void* addr)
168
    __attribute__ ((section (".2ram.flash_lock_block")));
169
int flash_unlock_block(void* block, int block_size, int blocks)
170
    __attribute__ ((section (".2ram.flash_unlock_block")));
171
 
172
//----------------------------------------------------------------------------
173
// Initialize driver details
174
int
175
flash_hwr_init(void)
176
{
177
    int i;
178
    flash_data_t id[2];
179
 
180
    CYGHWR_FLASH_28FXXX_PLF_INIT();
181
 
182
    flash_dev_query(id);
183
 
184
    // Look through table for device data
185
    flash_dev_info = supported_devices;
186
    for (i = 0; i < NUM_DEVICES; i++) {
187
        if (flash_dev_info->device_id == id[1])
188
            break;
189
        flash_dev_info++;
190
    }
191
 
192
    // Did we find the device? If not, return error.
193
    if (NUM_DEVICES == i)
194
        return FLASH_ERR_DRV_WRONG_PART;
195
 
196
    // Hard wired for now
197
    flash_info.block_size = flash_dev_info->block_size;
198
    flash_info.blocks = flash_dev_info->block_count * CYGNUM_FLASH_SERIES;
199
    flash_info.start = (void *)CYGNUM_FLASH_BASE;
200
    flash_info.end = (void *)(CYGNUM_FLASH_BASE+ (flash_dev_info->device_size * CYGNUM_FLASH_SERIES));
201
 
202
    return FLASH_ERR_OK;
203
}
204
 
205
//----------------------------------------------------------------------------
206
// Map a hardware status to a package error
207
int
208
flash_hwr_map_error(int e)
209
{
210
    return e;
211
}
212
 
213
 
214
//----------------------------------------------------------------------------
215
// See if a range of FLASH addresses overlaps currently running code
216
bool
217
flash_code_overlaps(void *start, void *end)
218
{
219
    extern unsigned char _stext[], _etext[];
220
 
221
    return ((((unsigned long)&_stext >= (unsigned long)start) &&
222
             ((unsigned long)&_stext < (unsigned long)end)) ||
223
            (((unsigned long)&_etext >= (unsigned long)start) &&
224
             ((unsigned long)&_etext < (unsigned long)end)));
225
}
226
 
227
//----------------------------------------------------------------------------
228
// Flash Query
229
//
230
// Only reads the manufacturer and part number codes for the first
231
// device(s) in series. It is assumed that any devices in series
232
// will be of the same type.
233
 
234
void
235
flash_query(void* data)
236
{
237
    volatile flash_data_t *ROM;
238
    flash_data_t* id = (flash_data_t*) data;
239
    flash_data_t w;
240
 
241
    ROM = (volatile flash_data_t*) CYGNUM_FLASH_BASE;
242
 
243
    w = ROM[0];
244
 
245
    CYGHWR_FLASH_WRITE_ENABLE();
246
 
247
    ROM[0] = FLASH_Read_ID;
248
 
249
    // Manufacturers' code
250
    id[0] = ROM[0];
251
    // Part number
252
    id[1] = ROM[1];
253
 
254
    ROM[0] = FLASH_Reset;
255
 
256
    CYGHWR_FLASH_WRITE_DISABLE();
257
 
258
    // Stall, waiting for flash to return to read mode.
259
    while (w != ROM[0]);
260
}
261
 
262
//----------------------------------------------------------------------------
263
// Erase Block
264
int
265
flash_erase_block(void* block, unsigned int block_size)
266
{
267
    int res = FLASH_ERR_OK;
268
    int timeout;
269
    unsigned long len;
270
    int len_ix = 1;
271
    flash_data_t stat;
272
    volatile flash_data_t *ROM;
273
    volatile flash_data_t *b_p = (flash_data_t*) block;
274
    volatile flash_data_t *b_v;
275
    cyg_bool bootblock;
276
 
277
    ROM = FLASH_P2V((unsigned long)block & flash_dev_info->base_mask);
278
 
279
    // Is this the boot sector?
280
    bootblock = (flash_dev_info->bootblock &&
281
                 (flash_dev_info->bootblocks[0] == ((unsigned long)block - (unsigned long)ROM)));
282
    if (bootblock) {
283
        len = flash_dev_info->bootblocks[len_ix++];
284
    } else {
285
        len = flash_dev_info->block_size;
286
    }
287
 
288
    CYGHWR_FLASH_WRITE_ENABLE();
289
 
290
    while (len > 0) {
291
        b_v = FLASH_P2V(b_p);
292
 
293
        // Clear any error conditions
294
        ROM[0] = FLASH_Clear_Status;
295
 
296
        // Erase block
297
        ROM[0] = FLASH_Block_Erase;
298
        *b_v = FLASH_Confirm;
299
 
300
        timeout = 5000000;
301
        while(((stat = ROM[0]) & FLASH_Status_Ready) != FLASH_Status_Ready) {
302
            if (--timeout == 0) break;
303
        }
304
 
305
        // Restore ROM to "normal" mode
306
        ROM[0] = FLASH_Reset;
307
 
308
        if (stat & FLASH_ErrorMask) {
309
            if (!(stat & FLASH_ErrorErase)) {
310
                res = FLASH_ERR_HWR;    // Unknown error
311
             } else {
312
                if (stat & FLASH_ErrorLowVoltage)
313
                    res = FLASH_ERR_LOW_VOLTAGE;
314
                else if (stat & FLASH_ErrorLocked)
315
                    res = FLASH_ERR_PROTECT;
316
                else
317
                    res = FLASH_ERR_ERASE;
318
            }
319
        }
320
 
321
        // Check if block got erased
322
        while (len > 0) {
323
            b_v = FLASH_P2V(b_p++);
324
            if (*b_v != FLASH_BlankValue ) {
325
                // Only update return value if erase operation was OK
326
                if (FLASH_ERR_OK == res) res = FLASH_ERR_DRV_VERIFY;
327
                return res;
328
            }
329
            len -= sizeof(*b_p);
330
        }
331
 
332
        if (bootblock)
333
            len = flash_dev_info->bootblocks[len_ix++];
334
    }
335
 
336
    CYGHWR_FLASH_WRITE_DISABLE();
337
 
338
    return res;
339
}
340
 
341
//----------------------------------------------------------------------------
342
// Program Buffer
343
int
344
flash_program_buf(void* addr, void* data, int len,
345
                  unsigned long block_mask, int buffer_size)
346
{
347
    flash_data_t stat = 0;
348
    int timeout;
349
 
350
    volatile flash_data_t* ROM;
351
    volatile flash_data_t* BA;
352
    volatile flash_data_t* addr_v;
353
    volatile flash_data_t* addr_p = (flash_data_t*) addr;
354
    volatile flash_data_t* data_p = (flash_data_t*) data;
355
 
356
    int res = FLASH_ERR_OK;
357
 
358
    // Base address of device(s) being programmed.
359
    ROM = FLASH_P2V((unsigned long)addr & flash_dev_info->base_mask);
360
    BA = FLASH_P2V((unsigned long)addr & ~(flash_dev_info->block_size - 1));
361
 
362
    CYGHWR_FLASH_WRITE_ENABLE();
363
 
364
    // Clear any error conditions
365
    ROM[0] = FLASH_Clear_Status;
366
 
367
#ifdef CYGHWR_DEVS_FLASH_INTEL_BUFFERED_WRITES
368
    // FIXME: This code has not been adjusted to handle bootblock
369
    // parts yet.
370
    // FIXME: This code does not appear to work anymore
371
    if (0 && flash_dev_info->buffered_w) {
372
        int i, wc;
373
        // Write any big chunks first
374
        while (len >= buffer_size) {
375
            wc = buffer_size;
376
            if (wc > len) wc = len;
377
            len -= wc;
378
            wc = wc / ((CYGNUM_FLASH_WIDTH/8)*CYGNUM_FLASH_INTERLEAVE);  // Word count
379
            timeout = 5000000;
380
 
381
            *BA = FLASH_Write_Buffer;
382
            while(((stat = ROM[0]) & FLASH_Status_Ready) != FLASH_Status_Ready) {
383
                if (--timeout == 0) {
384
                    res = FLASH_ERR_DRV_TIMEOUT;
385
                    goto bad;
386
                }
387
                *BA = FLASH_Write_Buffer;
388
            }
389
            *BA = FLASHWORD(wc-1);  // Count is 0..N-1
390
            for (i = 0; i < wc;  i++) {
391
                addr_v = FLASH_P2V(addr_p++);
392
                *addr_v = *data_p++;
393
            }
394
            *BA = FLASH_Confirm;
395
 
396
            ROM[0] = FLASH_Read_Status;
397
            timeout = 5000000;
398
            while(((stat = ROM[0]) & FLASH_Status_Ready) != FLASH_Status_Ready) {
399
                if (--timeout == 0) {
400
                    res = FLASH_ERR_DRV_TIMEOUT;
401
                    goto bad;
402
                }
403
            }
404
        }
405
    }
406
#endif // CYGHWR_DEVS_FLASH_INTEL_BUFFERED_WRITES
407
 
408
    while (len > 0) {
409
        addr_v = FLASH_P2V(addr_p++);
410
        ROM[0] = FLASH_Program;
411
        *addr_v = *data_p;
412
        timeout = 5000000;
413
        while(((stat = ROM[0]) & FLASH_Status_Ready) != FLASH_Status_Ready) {
414
            if (--timeout == 0) {
415
                res = FLASH_ERR_DRV_TIMEOUT;
416
                goto bad;
417
            }
418
        }
419
        if (stat & FLASH_ErrorMask) {
420
            if (!(stat & FLASH_ErrorProgram))
421
                res = FLASH_ERR_HWR;    // Unknown error
422
            else {
423
                if (stat & FLASH_ErrorLowVoltage)
424
                    res = FLASH_ERR_LOW_VOLTAGE;
425
                else if (stat & FLASH_ErrorLocked)
426
                    res = FLASH_ERR_PROTECT;
427
                else
428
                    res = FLASH_ERR_PROGRAM;
429
            }
430
            break;
431
        }
432
        ROM[0] = FLASH_Clear_Status;
433
        ROM[0] = FLASH_Reset;
434
        if (*addr_v != *data_p++) {
435
            res = FLASH_ERR_DRV_VERIFY;
436
            break;
437
        }
438
        len -= sizeof( flash_data_t );
439
    }
440
 
441
    // Restore ROM to "normal" mode
442
 bad:
443
    ROM[0] = FLASH_Reset;
444
 
445
    CYGHWR_FLASH_WRITE_DISABLE();
446
 
447
    // Ideally, we'd want to return not only the failure code, but also
448
    // the address/device that reported the error.
449
    return res;
450
}
451
 
452
#ifdef CYGHWR_IO_FLASH_BLOCK_LOCKING
453
//----------------------------------------------------------------------------
454
// Lock block
455
int
456
flash_lock_block(void* block)
457
{
458
    volatile flash_data_t *ROM;
459
    int res = FLASH_ERR_OK;
460
    flash_data_t state;
461
    int timeout = 5000000;
462
    volatile flash_data_t* b_p = (flash_data_t*) block;
463
    volatile flash_data_t *b_v;
464
    cyg_bool bootblock;
465
    int len, len_ix = 1;
466
 
467
    if (!flash_dev_info->locking)
468
        return res;
469
 
470
#ifdef DEBUG
471
    d_print("flash_lock_block %08x\n", block);
472
#endif
473
 
474
    ROM = (volatile flash_data_t*)((unsigned long)block & flash_dev_info->base_mask);
475
 
476
    // Is this the boot sector?
477
    bootblock = (flash_dev_info->bootblock &&
478
                 (flash_dev_info->bootblocks[0] == ((unsigned long)block - (unsigned long)ROM)));
479
    if (bootblock) {
480
        len = flash_dev_info->bootblocks[len_ix++];
481
    } else {
482
        len = flash_dev_info->block_size;
483
    }
484
 
485
    CYGHWR_FLASH_WRITE_ENABLE();
486
 
487
    while (len > 0) {
488
        b_v = FLASH_P2V(b_p);
489
 
490
        // Clear any error conditions
491
        ROM[0] = FLASH_Clear_Status;
492
 
493
        // Set lock bit
494
        *b_v = FLASH_Set_Lock;
495
        *b_v = FLASH_Set_Lock_Confirm;  // Confirmation
496
        while(((state = ROM[0]) & FLASH_Status_Ready) != FLASH_Status_Ready) {
497
            if (--timeout == 0) {
498
                res = FLASH_ERR_DRV_TIMEOUT;
499
                break;
500
            }
501
        }
502
 
503
        // Restore ROM to "normal" mode
504
        ROM[0] = FLASH_Reset;
505
 
506
        // Go to next block
507
        b_p += len / sizeof( flash_data_t );
508
        len = 0;
509
 
510
        if (FLASH_ErrorLock == (state & FLASH_ErrorLock))
511
            res = FLASH_ERR_LOCK;
512
 
513
        if (res != FLASH_ERR_OK)
514
            break;
515
 
516
        if (bootblock)
517
            len = flash_dev_info->bootblocks[len_ix++];
518
    }
519
 
520
    CYGHWR_FLASH_WRITE_DISABLE();
521
 
522
    return res;
523
}
524
 
525
//----------------------------------------------------------------------------
526
// Unlock block
527
 
528
int
529
flash_unlock_block(void* block, int block_size, int blocks)
530
{
531
    volatile flash_data_t *ROM;
532
    int res = FLASH_ERR_OK;
533
    flash_data_t state;
534
    int timeout = 5000000;
535
    volatile flash_data_t* b_p = (flash_data_t*) block;
536
    volatile flash_data_t *b_v;
537
 
538
#if (defined(CYGHWR_DEVS_FLASH_SHARP_LH28F016SCT_Z4) || defined(CYGHWR_DEVS_FLASH_SHARP_LH28F016SCT_95) )
539
    // The Sharp device follows all the same rules as the Intel 28x part,
540
    // except that the unlocking mechanism unlocks all blocks at once.  This
541
    // is the way the Strata part seems to work.  I will replace the
542
    // flash_unlock_block function with one similar to the Strata function.
543
    // As the Sharp part does not have the bootlock characteristics, I
544
    // will ignore them.
545
//
546
// The difficulty with this operation is that the hardware does not support
547
// unlocking single blocks.  However, the logical layer would like this to
548
// be the case, so this routine emulates it.  The hardware can clear all of
549
// the locks in the device at once.  This routine will use that approach and
550
// then reset the regions which are known to be locked.
551
//
552
 
553
#define MAX_FLASH_BLOCKS (flash_dev_info->block_count * CYGNUM_FLASH_SERIES)
554
 
555
    unsigned char is_locked[MAX_FLASH_BLOCKS];
556
    int i;
557
 
558
    // Get base address and map addresses to virtual addresses
559
#ifdef DEBUG
560
    d_print("\nNow inside low level driver\n");
561
#endif
562
    ROM = (volatile flash_data_t*) CYGNUM_FLASH_BASE;
563
    block = FLASH_P2V(block);
564
 
565
    // Clear any error conditions
566
    ROM[0] = FLASH_Clear_Status;
567
 
568
    // Get current block lock state.  This needs to access each block on
569
    // the device so currently locked blocks can be re-locked.
570
    b_p = ROM;
571
    for (i = 0;  i < blocks;  i++) {
572
        b_v = FLASH_P2V( b_p );
573
        *b_v = FLASH_Read_ID;
574
        if (b_v == block) {
575
            is_locked[i] = 0;
576
        } else {
577
            if(b_v[2]){ /* it is possible that one of the interleaved devices
578
                         * is locked, but others are not.  Coming out of this
579
                         * function, if one was locked, all will be locked.
580
                         */
581
                is_locked[i] = 1;
582
            }else{
583
                is_locked[i] = 0;
584
            }
585
        }
586
#ifdef DEBUG
587
#endif
588
        b_p += block_size / sizeof(*b_p);
589
    }
590
    ROM[0] = FLASH_Reset;
591
#ifdef DEBUG
592
    for (i = 0;  i < blocks;  i++) {
593
        d_print("\nblock %d  %s", i,
594
                is_locked[i] ? "LOCKED" : "UNLOCKED");
595
    }
596
    d_print("\n");
597
#endif
598
 
599
    // Clears all lock bits
600
    ROM[0] = FLASH_Clear_Lock;
601
    ROM[0] = FLASH_Clear_Lock_Confirm;  // Confirmation
602
    timeout = 5000000;
603
    while(((state = ROM[0]) & FLASH_Status_Ready) != FLASH_Status_Ready) {
604
        if (--timeout == 0) break;
605
    }
606
 
607
    // Restore the lock state
608
    b_p = ROM;
609
    for (i = 0;  i < blocks;  i++) {
610
        b_v = FLASH_P2V( b_p );
611
        if (is_locked[i]) {
612
            *b_v = FLASH_Set_Lock;
613
            *b_v = FLASH_Set_Lock_Confirm;  // Confirmation
614
            timeout = 5000000;
615
            while(((state = ROM[0]) & FLASH_Status_Ready)
616
                  != FLASH_Status_Ready) {
617
                if (--timeout == 0){
618
                    res = FLASH_ERR_DRV_TIMEOUT;
619
                    break;
620
                }
621
            }
622
            if (FLASH_ErrorLock == (state & FLASH_ErrorLock))
623
                res = FLASH_ERR_LOCK;
624
 
625
            if (res != FLASH_ERR_OK)
626
                break;
627
 
628
        }
629
        b_p += block_size / sizeof(*b_p);
630
    }
631
 
632
    // Restore ROM to "normal" mode
633
    ROM[0] = FLASH_Reset;
634
 
635
    return res;
636
 
637
#else // not CYGHWR_DEVS_FLASH_SHARP_LH28F016SCT_Z4
638
 
639
    cyg_bool bootblock;
640
    int len, len_ix = 1;
641
 
642
    if (!flash_dev_info->locking)
643
        return res;
644
 
645
    ROM = (volatile flash_data_t*)((unsigned long)block & flash_dev_info->base_mask);
646
 
647
#ifdef DEBUG
648
    d_print("flash_unlock_block dev %08x block %08x size %08x count %08x\n", ROM, block, block_size, blocks);
649
#endif
650
 
651
    // Is this the boot sector?
652
    bootblock = (flash_dev_info->bootblock &&
653
                 (flash_dev_info->bootblocks[0] == ((unsigned long)block - (unsigned long)ROM)));
654
    if (bootblock) {
655
        len = flash_dev_info->bootblocks[len_ix++];
656
    } else {
657
        len = flash_dev_info->block_size;
658
    }
659
 
660
    CYGHWR_FLASH_WRITE_ENABLE();
661
 
662
    while (len > 0) {
663
 
664
        b_v = FLASH_P2V(b_p);
665
 
666
        // Clear any error conditions
667
        ROM[0] = FLASH_Clear_Status;
668
 
669
        // Clear lock bit
670
        *b_v = FLASH_Clear_Lock;
671
        *b_v = FLASH_Clear_Lock_Confirm;  // Confirmation
672
        while(((state = ROM[0]) & FLASH_Status_Ready) != FLASH_Status_Ready) {
673
            if (--timeout == 0) {
674
                res = FLASH_ERR_DRV_TIMEOUT;
675
                break;
676
            }
677
        }
678
 
679
        // Restore ROM to "normal" mode
680
        ROM[0] = FLASH_Reset;
681
 
682
        // Go to next block
683
        b_p += len / sizeof( flash_data_t );
684
        len = 0;
685
 
686
        if (FLASH_ErrorLock == (state & FLASH_ErrorLock))
687
            res = FLASH_ERR_LOCK;
688
 
689
        if (res != FLASH_ERR_OK)
690
            break;
691
 
692
        if (bootblock)
693
            len = flash_dev_info->bootblocks[len_ix++];
694
    }
695
 
696
    CYGHWR_FLASH_WRITE_DISABLE();
697
 
698
    return res;
699
 
700
    // FIXME: Unlocking need to support some other parts in the future
701
    // as well which take a little more diddling.
702
#if 0
703
//
704
// The difficulty with this operation is that the hardware does not support
705
// unlocking single blocks.  However, the logical layer would like this to
706
// be the case, so this routine emulates it.  The hardware can clear all of
707
// the locks in the device at once.  This routine will use that approach and
708
// then reset the regions which are known to be locked.
709
//
710
 
711
#define MAX_FLASH_BLOCKS (flash_dev_info->block_count * CYGNUM_FLASH_SERIES)
712
 
713
    unsigned char is_locked[MAX_FLASH_BLOCKS];
714
 
715
    // Get base address and map addresses to virtual addresses
716
    ROM = FLASH_P2V( CYGNUM_FLASH_BASE_MASK & (unsigned int)block );
717
    block = FLASH_P2V(block);
718
 
719
    // Clear any error conditions
720
    ROM[0] = FLASH_Clear_Status;
721
 
722
    // Get current block lock state.  This needs to access each block on
723
    // the device so currently locked blocks can be re-locked.
724
    bp = ROM;
725
    for (i = 0;  i < blocks;  i++) {
726
        bpv = FLASH_P2V( bp );
727
        *bpv = FLASH_Read_Query;
728
        if (bpv == block) {
729
            is_locked[i] = 0;
730
        } else {
731
            is_locked[i] = bpv[2];
732
        }
733
        bp += block_size / sizeof(*bp);
734
    }
735
 
736
    // Clears all lock bits
737
    ROM[0] = FLASH_Clear_Locks;
738
    ROM[0] = FLASH_Clear_Locks_Confirm;  // Confirmation
739
    timeout = 5000000;
740
    while(((stat = ROM[0]) & FLASH_Status_Ready) != FLASH_Status_Ready) {
741
        if (--timeout == 0) break;
742
    }
743
 
744
    // Restore the lock state
745
    bp = ROM;
746
    for (i = 0;  i < blocks;  i++) {
747
        bpv = FLASH_P2V( bp );
748
        if (is_locked[i]) {
749
            *bpv = FLASH_Set_Lock;
750
            *bpv = FLASH_Set_Lock_Confirm;  // Confirmation
751
            timeout = 5000000;
752
            while(((stat = ROM[0]) & FLASH_Status_Ready) != FLASH_Status_Ready) {
753
                if (--timeout == 0) break;
754
            }
755
        }
756
        bp += block_size / sizeof(*bp);
757
    }
758
 
759
    // Restore ROM to "normal" mode
760
    ROM[0] = FLASH_Reset;
761
#endif
762
#endif // #CYGHWR_DEVS_FLASH_SHARP_LH28F016SCT_Z4
763
}
764
#endif // CYGHWR_IO_FLASH_BLOCK_LOCKING
765
 
766
#endif // CYGONCE_DEVS_FLASH_INTEL_28FXXX_INL

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.