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#ifndef CYGONCE_MIPS_VRC437X_SERIAL_H
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#define CYGONCE_MIPS_VRC437X_SERIAL_H
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// ====================================================================
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//
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// vrc437x_serial.h
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//
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// Device I/O - Description of Mips VRC437X serial hardware
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//
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// ====================================================================
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//####ECOSGPLCOPYRIGHTBEGIN####
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// -------------------------------------------
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// This file is part of eCos, the Embedded Configurable Operating System.
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// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
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//
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// eCos is free software; you can redistribute it and/or modify it under
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// the terms of the GNU General Public License as published by the Free
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// Software Foundation; either version 2 or (at your option) any later version.
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//
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// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// for more details.
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//
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// You should have received a copy of the GNU General Public License along
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// with eCos; if not, write to the Free Software Foundation, Inc.,
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// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
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//
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// As a special exception, if other files instantiate templates or use macros
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// or inline functions from this file, or you compile this file and link it
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// with other works to produce a work based on this file, this file does not
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// by itself cause the resulting work to be covered by the GNU General Public
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// License. However the source code for this file must still be made available
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// in accordance with section (3) of the GNU General Public License.
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//
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// This exception does not invalidate any other reasons why a work based on
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// this file might be covered by the GNU General Public License.
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//
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// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
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// at http://sources.redhat.com/ecos/ecos-license/
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// -------------------------------------------
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//####ECOSGPLCOPYRIGHTEND####
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// ====================================================================
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//#####DESCRIPTIONBEGIN####
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//
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// Author(s): gthomas
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// Contributors: gthomas
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// Date: 1999-04-15
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// Purpose: Internal interfaces for serial I/O drivers
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// Description:
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//
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//####DESCRIPTIONEND####
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//
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// ====================================================================
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// Description of serial ports on Mips VRC437X
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// Based on Zilog 85C30 SCC
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struct serial_port {
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unsigned char _byte[16];
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};
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#define scc_ctl _byte[0]
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#define scc_dat _byte[8]
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#define R0 0 /* Register selects */
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#define R1 1
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#define R2 2
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#define R3 3
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#define R4 4
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#define R5 5
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#define R6 6
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#define R7 7
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#define R8 8
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#define R9 9
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#define R10 10
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#define R11 11
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#define R12 12
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#define R13 13
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#define R14 14
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#define R15 15
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/* Write Register 0 */
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#define WR0_NullCode 0x00 /* Null Code */
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#define WR0_PointHigh 0x08 /* Select upper half of registers */
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#define WR0_ResExtInt 0x10 /* Reset Ext. Status Interrupts */
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#define WR0_SendAbort 0x18 /* HDLC Abort */
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#define WR0_ResRxIntFC 0x20 /* Reset RxINT on First Character */
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#define WR0_ResTxP 0x28 /* Reset TxINT Pending */
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#define WR0_ErrReset 0x30 /* Error Reset */
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#define WR0_ResHiIUS 0x38 /* Reset highest IUS */
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#define WR0_ResRxCRC 0x40 /* Reset Rx CRC Checker */
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#define WR0_ResTxCRC 0x80 /* Reset Tx CRC Checker */
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#define WR0_ResEOMlatch 0xC0 /* Reset EOM latch */
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/* Write Register 1 */
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#define WR1_ExtIntEnab 0x01 /* Ext Int Enable */
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#define WR1_TxIntEnab 0x02 /* Tx Int Enable */
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#define WR1_ParSpec 0x04 /* Parity is special condition */
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#define WR1_RxIntDisab 0x00 /* Rx Int Disable */
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#define WR1_RxIntFCE 0x08 /* Rx Int on First Character Only or Error */
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#define WR1_IntAllRx 0x10 /* Int on all Rx Characters or error */
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#define WR1_IntErrRx 0x18 /* Int on error only */
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#define WR1_WtRdyRT 0x20 /* Wait/Ready on R/T */
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#define WR1_WtFnRdyFn 0x40 /* Wait/FN/Ready FN */
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#define WR1_WtRdyEnab 0x80 /* Wait/Ready Enable */
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/* Write Register #2 (Interrupt Vector) */
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/* Write Register 3 */
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#define WR3_RxEnable 0x01 /* Rx Enable */
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#define WR3_SyncInhibit 0x02 /* Sync Character Load Inhibit */
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#define WR3_AddrSearch 0x04 /* Address Search Mode (SDLC) */
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#define WR3_RxCRC_ENAB 0x08 /* Rx CRC Enable */
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#define WR3_EntHuntMode 0x10 /* Enter Hunt Mode */
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#define WR3_AutoEnab 0x20 /* Auto Enables */
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#define WR3_Rx5 0x00 /* Rx 5 Bits/Character */
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#define WR3_Rx7 0x40 /* Rx 7 Bits/Character */
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#define WR3_Rx6 0x80 /* Rx 6 Bits/Character */
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#define WR3_Rx8 0xc0 /* Rx 8 Bits/Character */
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#define WR3_RxNbitsMask 0xc0
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/* Write Register 4 */
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#define WR4_ParityEn 0x01 /* Parity Enable */
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#define WR4_ParityEven 0x02 /* Parity Even/Odd* */
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#define WR4_SyncEnable 0x00 /* Sync Modes Enable */
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#define WR4_SB1 0x04 /* 1 stop bit/char */
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#define WR4_SB15 0x08 /* 1.5 stop bits/char */
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#define WR4_SB2 0x0c /* 2 stop bits/char */
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#define WR4_SB_MASK 0x0c
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#define WR4_Monsync 0x00 /* 8 Bit Sync character */
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#define WR4_Bisync 0x10 /* 16 bit sync character */
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#define WR4_SDLC 0x20 /* SDLC Mode (01111110 Sync Flag) */
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#define WR4_EXtSync 0x30 /* External Sync Mode */
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#define WR4_X1CLK 0x00 /* x1 clock mode */
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#define WR4_X16CLK 0x40 /* x16 clock mode */
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#define WR4_X32CLK 0x80 /* x32 clock mode */
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#define WR4_X64CLK 0xC0 /* x64 clock mode */
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#define WR4_XCLK_MASK 0xC0
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/* Write Register 5 */
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#define WR5_TxCRCEnab 0x01 /* Tx CRC Enable */
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#define WR5_RTS 0x02 /* RTS */
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#define WR5_SDLC_CRC 0x04 /* SDLC/CRC-16 */
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#define WR5_TxEnable 0x08 /* Tx Enable */
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#define WR5_SendBreak 0x10 /* Send Break */
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#define WR5_Tx5 0x00 /* Tx 5 bits (or less)/character */
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#define WR5_Tx7 0x20 /* Tx 7 bits/character */
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#define WR5_Tx6 0x40 /* Tx 6 bits/character */
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#define WR5_Tx8 0x60 /* Tx 8 bits/character */
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#define WR5_TxNbitsMask 0x60
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#define WR5_DTR 0x80 /* DTR */
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/* Write Register 6 (Sync bits 0-7/SDLC Address Field) */
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/* Write Register 7 (Sync bits 8-15/SDLC 01111110) */
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/* Write Register 8 (transmit buffer) */
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/* Write Register 9 (Master interrupt control) */
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#define WR9_VIS 0x01 /* Vector Includes Status */
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#define WR9_NoVector 0x02 /* No Vector */
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#define WR9_DLC 0x04 /* Disable Lower Chain */
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#define WR9_MIE 0x08 /* Master Interrupt Enable */
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#define WR9_StatHi 0x10 /* Status high */
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#define WR9_NoReset 0x00 /* No reset on write to R9 */
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#define WR9_ResetB 0x40 /* Reset channel B */
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#define WR9_ResetA 0x80 /* Reset channel A */
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#define WR9_HwReset 0xc0 /* Force hardware reset */
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/* Write Register 10 (misc control bits) */
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#define WR10_Bit6 0x01 /* 6 bit/8bit sync */
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#define WR10_LoopMode 0x02 /* SDLC Loop mode */
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#define WR10_AbrtUnder 0x04 /* Abort/flag on SDLC xmit underrun */
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#define WR10_MarkIdle 0x08 /* Mark/flag on idle */
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#define WR10_GAOP 0x10 /* Go active on poll */
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#define WR10_NRZ 0x00 /* NRZ mode */
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#define WR10_NRZI 0x20 /* NRZI mode */
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#define WR10_FM1 0x40 /* FM1 (transition = 1) */
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#define WR10_FM0 0x60 /* FM0 (transition = 0) */
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#define WR10_CRCPS 0x80 /* CRC Preset I/O */
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/* Write Register 11 (Clock Mode control) */
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#define WR11_TRxCXT 0x00 /* TRxC = Xtal output */
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#define WR11_TRxCTC 0x01 /* TRxC = Transmit clock */
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#define WR11_TRxCBR 0x02 /* TRxC = BR Generator Output */
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#define WR11_TRxCDP 0x03 /* TRxC = DPLL output */
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#define WR11_TRxCOI 0x04 /* TRxC O/I */
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#define WR11_TxCRTxCP 0x00 /* Transmit clock = RTxC pin */
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#define WR11_TxCTRxCP 0x08 /* Transmit clock = TRxC pin */
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#define WR11_TxCBR 0x10 /* Transmit clock = BR Generator output */
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#define WR11_TxCDPLL 0x18 /* Transmit clock = DPLL output */
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#define WR11_RxCRTxCP 0x00 /* Receive clock = RTxC pin */
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#define WR11_RxCTRxCP 0x20 /* Receive clock = TRxC pin */
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#define WR11_RxCBR 0x40 /* Receive clock = BR Generator output */
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#define WR11_RxCDPLL 0x60 /* Receive clock = DPLL output */
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#define WR11_RTxCX 0x80 /* RTxC Xtal/No Xtal */
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/* Write Register 12 (lower byte of baud rate generator time constant) */
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/* Write Register 13 (upper byte of baud rate generator time constant) */
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/* Write Register 14 (Misc control bits) */
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#define WR14_BRenable 0x01 /* Baud rate generator enable */
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#define WR14_BRSRC 0x02 /* Baud rate generator source */
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#define WR14_DTRreq 0x04 /* DTR/Request function */
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#define WR14_AutoEcho 0x08 /* Auto Echo */
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#define WR14_LoopBack 0x10 /* Local loopback */
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#define WR14_Search 0x20 /* Enter search mode */
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#define WR14_RMC 0x40 /* Reset missing clock */
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#define WR14_NoDPLL 0x60 /* Disable DPLL */
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#define WR14_SSBR 0x80 /* Set DPLL source = BR generator */
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#define WR14_SSRTxC 0xa0 /* Set DPLL source = RTxC */
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#define WR14_SFMM 0xc0 /* Set FM mode */
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#define WR14_SNRZI 0xe0 /* Set NRZI mode */
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/* Write Register 15 (external/status interrupt control) */
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#define WR15_ZCIE 0x02 /* Zero count IE */
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#define WR15_DCDIE 0x08 /* DCD IE */
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#define WR15_SYNCIE 0x10 /* Sync/hunt IE */
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#define WR15_CTSIE 0x20 /* CTS IE */
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#define WR15_TxUIE 0x40 /* Tx Underrun/EOM IE */
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#define WR15_BRKIE 0x80 /* Break/Abort IE */
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/* Read Register 0 */
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#define RR0_RxAvail 0x01 /* Rx Character Available */
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#define RR0_Zcount 0x02 /* Zero count */
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#define RR0_TxEmpty 0x04 /* Tx Buffer empty */
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#define RR0_DCD 0x08 /* DCD */
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#define RR0_SyncHunt 0x10 /* Sync/hunt */
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#define RR0_CTS 0x20 /* CTS */
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#define RR0_TxEOM 0x40 /* Tx underrun */
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#define RR0_BrkAbort 0x80 /* Break/Abort */
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/* Read Register 1 */
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#define RR1_AllSent 0x01 /* All sent */
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/* Residue Data for 8 Rx bits/char programmed */
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#define RR1_RES3 0x08 /* 0/3 */
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#define RR1_RES4 0x04 /* 0/4 */
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#define RR1_RES5 0x0c /* 0/5 */
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#define RR1_RES6 0x02 /* 0/6 */
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#define RR1_RES7 0x0a /* 0/7 */
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#define RR1_RES8 0x06 /* 0/8 */
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#define RR1_RES18 0x0e /* 1/8 */
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#define RR1_RES28 0x00 /* 2/8 */
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/* Special Rx Condition Interrupts */
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#define RR1_PariryError 0x10 /* Parity error */
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#define RR1_RxOverrun 0x20 /* Rx Overrun Error */
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#define RR1_FrameError 0x40 /* CRC/Framing Error */
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#define RR1_EndOfFrame 0x80 /* End of Frame (SDLC) */
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262 |
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/* Read Register 2 (channel b only) - Interrupt vector */
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263 |
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/* Read Register 3 (interrupt pending register) ch a only */
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#define RR3_BExt 0x01 /* Channel B Ext/Stat IP */
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#define RR3_BTxIP 0x02 /* Channel B Tx IP */
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#define RR3_BRxIP 0x04 /* Channel B Rx IP */
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#define RR3_AExt 0x08 /* Channel A Ext/Stat IP */
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#define RR3_ATxIP 0x10 /* Channel A Tx IP */
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#define RR3_ARxIP 0x20 /* Channel A Rx IP */
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272 |
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/* Read Register 8 (receive data register) */
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273 |
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274 |
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/* Read Register 10 (misc status bits) */
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275 |
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#define RR10_OnLoop 0x02 /* On loop */
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#define RR10_LoopSend 0x10 /* Loop sending */
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#define RR10_Clk2Mis 0x40 /* Two clocks missing */
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278 |
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#define RR10_Clk1Mis 0x80 /* One clock missing */
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279 |
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280 |
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/* Read Register 12 (lower byte of baud rate generator constant) */
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281 |
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282 |
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/* Read Register 13 (upper byte of baud rate generator constant) */
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283 |
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284 |
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/* Read Register 15 (value of WR 15) */
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285 |
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286 |
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#define BRTC(brate) (( ((unsigned) DUART_CLOCK) / (2*(brate)*SCC_CLKMODE_TC)) - 2)
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#define DUART_CLOCK 4915200 /* Z8530 duart */
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#define SCC_CLKMODE_TC 16 /* Always run x16 clock for async modes */
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290 |
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static unsigned char select_word_length_WR3[] = {
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WR3_Rx5, // 5 bits / word (char)
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WR3_Rx6,
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WR3_Rx7,
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WR3_Rx8
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};
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static unsigned char select_word_length_WR5[] = {
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WR5_Tx5, // 5 bits / word (char)
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WR5_Tx6,
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WR5_Tx7,
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WR5_Tx8
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};
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303 |
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304 |
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static unsigned char select_stop_bits[] = {
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0,
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WR4_SB1, // 1 stop bit
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WR4_SB15, // 1.5 stop bit
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WR4_SB2 // 2 stop bits
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};
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310 |
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311 |
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static unsigned char select_parity[] = {
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312 |
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0, // No parity
|
313 |
|
|
WR4_ParityEn | WR4_ParityEven, // Even parity
|
314 |
|
|
WR4_ParityEn, // Odd parity
|
315 |
|
|
0xFF, // Mark parity
|
316 |
|
|
0xFF, // Space parity
|
317 |
|
|
};
|
318 |
|
|
|
319 |
|
|
static cyg_int32 select_baud[] = {
|
320 |
|
|
0, // Unused
|
321 |
|
|
50, // 50
|
322 |
|
|
75, // 75
|
323 |
|
|
110, // 110
|
324 |
|
|
0, // 134.5
|
325 |
|
|
150, // 150
|
326 |
|
|
200, // 200
|
327 |
|
|
300, // 300
|
328 |
|
|
600, // 600
|
329 |
|
|
1200, // 1200
|
330 |
|
|
1800, // 1800
|
331 |
|
|
2400, // 2400
|
332 |
|
|
3600, // 3600
|
333 |
|
|
4800, // 4800
|
334 |
|
|
7200, // 7200
|
335 |
|
|
9600, // 9600
|
336 |
|
|
14400, // 14400
|
337 |
|
|
19200, // 19200
|
338 |
|
|
38400, // 38400
|
339 |
|
|
0, // 57600
|
340 |
|
|
0, // 115200
|
341 |
|
|
0, // 230400
|
342 |
|
|
};
|
343 |
|
|
|
344 |
|
|
#endif // CYGONCE_MIPS_VRC437X_SERIAL_H
|