OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [rtos/] [ecos-2.0/] [packages/] [devs/] [serial/] [mips/] [vrc437x/] [v2_0/] [src/] [vrc437x_serial.h] - Blame information for rev 454

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 27 unneback
#ifndef CYGONCE_MIPS_VRC437X_SERIAL_H
2
#define CYGONCE_MIPS_VRC437X_SERIAL_H
3
 
4
// ====================================================================
5
//
6
//      vrc437x_serial.h
7
//
8
//      Device I/O - Description of Mips VRC437X serial hardware
9
//
10
// ====================================================================
11
//####ECOSGPLCOPYRIGHTBEGIN####
12
// -------------------------------------------
13
// This file is part of eCos, the Embedded Configurable Operating System.
14
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
15
//
16
// eCos is free software; you can redistribute it and/or modify it under
17
// the terms of the GNU General Public License as published by the Free
18
// Software Foundation; either version 2 or (at your option) any later version.
19
//
20
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
21
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
22
// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
23
// for more details.
24
//
25
// You should have received a copy of the GNU General Public License along
26
// with eCos; if not, write to the Free Software Foundation, Inc.,
27
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
28
//
29
// As a special exception, if other files instantiate templates or use macros
30
// or inline functions from this file, or you compile this file and link it
31
// with other works to produce a work based on this file, this file does not
32
// by itself cause the resulting work to be covered by the GNU General Public
33
// License. However the source code for this file must still be made available
34
// in accordance with section (3) of the GNU General Public License.
35
//
36
// This exception does not invalidate any other reasons why a work based on
37
// this file might be covered by the GNU General Public License.
38
//
39
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
40
// at http://sources.redhat.com/ecos/ecos-license/
41
// -------------------------------------------
42
//####ECOSGPLCOPYRIGHTEND####
43
// ====================================================================
44
//#####DESCRIPTIONBEGIN####
45
//
46
// Author(s):           gthomas
47
// Contributors:        gthomas
48
// Date:        1999-04-15
49
// Purpose:     Internal interfaces for serial I/O drivers
50
// Description:
51
//
52
//####DESCRIPTIONEND####
53
//
54
// ====================================================================
55
 
56
// Description of serial ports on Mips VRC437X
57
//   Based on Zilog 85C30 SCC
58
 
59
struct serial_port {
60
    unsigned char _byte[16];
61
};
62
 
63
#define scc_ctl _byte[0]
64
#define scc_dat _byte[8]
65
 
66
#define R0      0                /* Register selects */
67
#define R1      1
68
#define R2      2
69
#define R3      3
70
#define R4      4
71
#define R5      5
72
#define R6      6
73
#define R7      7
74
#define R8      8
75
#define R9      9
76
#define R10     10
77
#define R11     11
78
#define R12     12
79
#define R13     13
80
#define R14     14
81
#define R15     15
82
 
83
/* Write Register 0 */
84
#define WR0_NullCode    0x00    /* Null Code */
85
#define WR0_PointHigh   0x08    /* Select upper half of registers */
86
#define WR0_ResExtInt   0x10    /* Reset Ext. Status Interrupts */
87
#define WR0_SendAbort   0x18    /* HDLC Abort */
88
#define WR0_ResRxIntFC  0x20    /* Reset RxINT on First Character */
89
#define WR0_ResTxP      0x28    /* Reset TxINT Pending */
90
#define WR0_ErrReset    0x30    /* Error Reset */
91
#define WR0_ResHiIUS    0x38    /* Reset highest IUS */
92
 
93
#define WR0_ResRxCRC    0x40    /* Reset Rx CRC Checker */
94
#define WR0_ResTxCRC    0x80    /* Reset Tx CRC Checker */
95
#define WR0_ResEOMlatch 0xC0    /* Reset EOM latch */
96
 
97
/* Write Register 1 */
98
 
99
#define WR1_ExtIntEnab  0x01    /* Ext Int Enable */
100
#define WR1_TxIntEnab   0x02    /* Tx Int Enable */
101
#define WR1_ParSpec     0x04    /* Parity is special condition */
102
 
103
#define WR1_RxIntDisab  0x00    /* Rx Int Disable */
104
#define WR1_RxIntFCE    0x08    /* Rx Int on First Character Only or Error */
105
#define WR1_IntAllRx    0x10    /* Int on all Rx Characters or error */
106
#define WR1_IntErrRx    0x18    /* Int on error only */
107
 
108
#define WR1_WtRdyRT     0x20    /* Wait/Ready on R/T */
109
#define WR1_WtFnRdyFn   0x40    /* Wait/FN/Ready FN */
110
#define WR1_WtRdyEnab   0x80    /* Wait/Ready Enable */
111
 
112
/* Write Register #2 (Interrupt Vector) */
113
 
114
/* Write Register 3 */
115
 
116
#define WR3_RxEnable    0x01    /* Rx Enable */
117
#define WR3_SyncInhibit 0x02    /* Sync Character Load Inhibit */
118
#define WR3_AddrSearch  0x04    /* Address Search Mode (SDLC) */
119
#define WR3_RxCRC_ENAB  0x08    /* Rx CRC Enable */
120
#define WR3_EntHuntMode 0x10    /* Enter Hunt Mode */
121
#define WR3_AutoEnab    0x20    /* Auto Enables */
122
#define WR3_Rx5         0x00    /* Rx 5 Bits/Character */
123
#define WR3_Rx7         0x40    /* Rx 7 Bits/Character */
124
#define WR3_Rx6         0x80    /* Rx 6 Bits/Character */
125
#define WR3_Rx8         0xc0    /* Rx 8 Bits/Character */
126
#define WR3_RxNbitsMask 0xc0
127
 
128
/* Write Register 4 */
129
 
130
#define WR4_ParityEn    0x01    /* Parity Enable */
131
#define WR4_ParityEven  0x02    /* Parity Even/Odd* */
132
 
133
#define WR4_SyncEnable  0x00    /* Sync Modes Enable */
134
#define WR4_SB1         0x04    /* 1 stop bit/char */
135
#define WR4_SB15        0x08    /* 1.5 stop bits/char */
136
#define WR4_SB2         0x0c    /* 2 stop bits/char */
137
#define WR4_SB_MASK     0x0c
138
 
139
#define WR4_Monsync     0x00    /* 8 Bit Sync character */
140
#define WR4_Bisync      0x10    /* 16 bit sync character */
141
#define WR4_SDLC        0x20    /* SDLC Mode (01111110 Sync Flag) */
142
#define WR4_EXtSync     0x30    /* External Sync Mode */
143
 
144
#define WR4_X1CLK       0x00    /* x1 clock mode */
145
#define WR4_X16CLK      0x40    /* x16 clock mode */
146
#define WR4_X32CLK      0x80    /* x32 clock mode */
147
#define WR4_X64CLK      0xC0    /* x64 clock mode */
148
#define WR4_XCLK_MASK   0xC0
149
 
150
/* Write Register 5 */
151
 
152
#define WR5_TxCRCEnab   0x01    /* Tx CRC Enable */
153
#define WR5_RTS         0x02    /* RTS */
154
#define WR5_SDLC_CRC    0x04    /* SDLC/CRC-16 */
155
#define WR5_TxEnable    0x08    /* Tx Enable */
156
#define WR5_SendBreak   0x10    /* Send Break */
157
#define WR5_Tx5         0x00    /* Tx 5 bits (or less)/character */
158
#define WR5_Tx7         0x20    /* Tx 7 bits/character */
159
#define WR5_Tx6         0x40    /* Tx 6 bits/character */
160
#define WR5_Tx8         0x60    /* Tx 8 bits/character */
161
#define WR5_TxNbitsMask 0x60
162
#define WR5_DTR         0x80    /* DTR */
163
 
164
/* Write Register 6 (Sync bits 0-7/SDLC Address Field) */
165
 
166
/* Write Register 7 (Sync bits 8-15/SDLC 01111110) */
167
 
168
/* Write Register 8 (transmit buffer) */
169
 
170
/* Write Register 9 (Master interrupt control) */
171
#define WR9_VIS         0x01    /* Vector Includes Status */
172
#define WR9_NoVector    0x02    /* No Vector */
173
#define WR9_DLC         0x04    /* Disable Lower Chain */
174
#define WR9_MIE         0x08    /* Master Interrupt Enable */
175
#define WR9_StatHi      0x10    /* Status high */
176
#define WR9_NoReset     0x00    /* No reset on write to R9 */
177
#define WR9_ResetB      0x40    /* Reset channel B */
178
#define WR9_ResetA      0x80    /* Reset channel A */
179
#define WR9_HwReset     0xc0    /* Force hardware reset */
180
 
181
/* Write Register 10 (misc control bits) */
182
#define WR10_Bit6       0x01    /* 6 bit/8bit sync */
183
#define WR10_LoopMode   0x02    /* SDLC Loop mode */
184
#define WR10_AbrtUnder  0x04    /* Abort/flag on SDLC xmit underrun */
185
#define WR10_MarkIdle   0x08    /* Mark/flag on idle */
186
#define WR10_GAOP       0x10    /* Go active on poll */
187
#define WR10_NRZ        0x00    /* NRZ mode */
188
#define WR10_NRZI       0x20    /* NRZI mode */
189
#define WR10_FM1        0x40    /* FM1 (transition = 1) */
190
#define WR10_FM0        0x60    /* FM0 (transition = 0) */
191
#define WR10_CRCPS      0x80    /* CRC Preset I/O */
192
 
193
/* Write Register 11 (Clock Mode control) */
194
#define WR11_TRxCXT     0x00    /* TRxC = Xtal output */
195
#define WR11_TRxCTC     0x01    /* TRxC = Transmit clock */
196
#define WR11_TRxCBR     0x02    /* TRxC = BR Generator Output */
197
#define WR11_TRxCDP     0x03    /* TRxC = DPLL output */
198
#define WR11_TRxCOI     0x04    /* TRxC O/I */
199
#define WR11_TxCRTxCP   0x00    /* Transmit clock = RTxC pin */
200
#define WR11_TxCTRxCP   0x08    /* Transmit clock = TRxC pin */
201
#define WR11_TxCBR      0x10    /* Transmit clock = BR Generator output */
202
#define WR11_TxCDPLL    0x18    /* Transmit clock = DPLL output */
203
#define WR11_RxCRTxCP   0x00    /* Receive clock = RTxC pin */
204
#define WR11_RxCTRxCP   0x20    /* Receive clock = TRxC pin */
205
#define WR11_RxCBR      0x40    /* Receive clock = BR Generator output */
206
#define WR11_RxCDPLL    0x60    /* Receive clock = DPLL output */
207
#define WR11_RTxCX      0x80    /* RTxC Xtal/No Xtal */
208
 
209
/* Write Register 12 (lower byte of baud rate generator time constant) */
210
 
211
/* Write Register 13 (upper byte of baud rate generator time constant) */
212
 
213
/* Write Register 14 (Misc control bits) */
214
#define WR14_BRenable   0x01    /* Baud rate generator enable */
215
#define WR14_BRSRC      0x02    /* Baud rate generator source */
216
#define WR14_DTRreq     0x04    /* DTR/Request function */
217
#define WR14_AutoEcho   0x08    /* Auto Echo */
218
#define WR14_LoopBack   0x10    /* Local loopback */
219
#define WR14_Search     0x20    /* Enter search mode */
220
#define WR14_RMC        0x40    /* Reset missing clock */
221
#define WR14_NoDPLL     0x60    /* Disable DPLL */
222
#define WR14_SSBR       0x80    /* Set DPLL source = BR generator */
223
#define WR14_SSRTxC     0xa0    /* Set DPLL source = RTxC */
224
#define WR14_SFMM       0xc0    /* Set FM mode */
225
#define WR14_SNRZI      0xe0    /* Set NRZI mode */
226
 
227
/* Write Register 15 (external/status interrupt control) */
228
#define WR15_ZCIE       0x02    /* Zero count IE */
229
#define WR15_DCDIE      0x08    /* DCD IE */
230
#define WR15_SYNCIE     0x10    /* Sync/hunt IE */
231
#define WR15_CTSIE      0x20    /* CTS IE */
232
#define WR15_TxUIE      0x40    /* Tx Underrun/EOM IE */
233
#define WR15_BRKIE      0x80    /* Break/Abort IE */
234
 
235
/* Read Register 0 */
236
#define RR0_RxAvail     0x01    /* Rx Character Available */
237
#define RR0_Zcount      0x02    /* Zero count */
238
#define RR0_TxEmpty     0x04    /* Tx Buffer empty */
239
#define RR0_DCD         0x08    /* DCD */
240
#define RR0_SyncHunt    0x10    /* Sync/hunt */
241
#define RR0_CTS         0x20    /* CTS */
242
#define RR0_TxEOM       0x40    /* Tx underrun */
243
#define RR0_BrkAbort    0x80    /* Break/Abort */
244
 
245
/* Read Register 1 */
246
#define RR1_AllSent     0x01    /* All sent */
247
/* Residue Data for 8 Rx bits/char programmed */
248
#define RR1_RES3        0x08    /* 0/3 */
249
#define RR1_RES4        0x04    /* 0/4 */
250
#define RR1_RES5        0x0c    /* 0/5 */
251
#define RR1_RES6        0x02    /* 0/6 */
252
#define RR1_RES7        0x0a    /* 0/7 */
253
#define RR1_RES8        0x06    /* 0/8 */
254
#define RR1_RES18       0x0e    /* 1/8 */
255
#define RR1_RES28       0x00    /* 2/8 */
256
/* Special Rx Condition Interrupts */
257
#define RR1_PariryError 0x10    /* Parity error */
258
#define RR1_RxOverrun   0x20    /* Rx Overrun Error */
259
#define RR1_FrameError  0x40    /* CRC/Framing Error */
260
#define RR1_EndOfFrame  0x80    /* End of Frame (SDLC) */
261
 
262
/* Read Register 2 (channel b only) - Interrupt vector */
263
 
264
/* Read Register 3 (interrupt pending register) ch a only */
265
#define RR3_BExt        0x01            /* Channel B Ext/Stat IP */
266
#define RR3_BTxIP       0x02            /* Channel B Tx IP */
267
#define RR3_BRxIP       0x04            /* Channel B Rx IP */
268
#define RR3_AExt        0x08            /* Channel A Ext/Stat IP */
269
#define RR3_ATxIP       0x10            /* Channel A Tx IP */
270
#define RR3_ARxIP       0x20            /* Channel A Rx IP */
271
 
272
/* Read Register 8 (receive data register) */
273
 
274
/* Read Register 10  (misc status bits) */
275
#define RR10_OnLoop     0x02            /* On loop */
276
#define RR10_LoopSend   0x10            /* Loop sending */
277
#define RR10_Clk2Mis    0x40            /* Two clocks missing */
278
#define RR10_Clk1Mis    0x80            /* One clock missing */
279
 
280
/* Read Register 12 (lower byte of baud rate generator constant) */
281
 
282
/* Read Register 13 (upper byte of baud rate generator constant) */
283
 
284
/* Read Register 15 (value of WR 15) */
285
 
286
#define BRTC(brate) (( ((unsigned) DUART_CLOCK) / (2*(brate)*SCC_CLKMODE_TC)) - 2)
287
#define DUART_CLOCK          4915200         /* Z8530 duart */
288
#define SCC_CLKMODE_TC       16              /* Always run x16 clock for async modes */
289
 
290
static unsigned char select_word_length_WR3[] = {
291
    WR3_Rx5,            // 5 bits / word (char)
292
    WR3_Rx6,
293
    WR3_Rx7,
294
    WR3_Rx8
295
};
296
 
297
static unsigned char select_word_length_WR5[] = {
298
    WR5_Tx5,            // 5 bits / word (char)
299
    WR5_Tx6,
300
    WR5_Tx7,
301
    WR5_Tx8
302
};
303
 
304
static unsigned char select_stop_bits[] = {
305
    0,
306
    WR4_SB1,    // 1 stop bit
307
    WR4_SB15,   // 1.5 stop bit
308
    WR4_SB2     // 2 stop bits
309
};
310
 
311
static unsigned char select_parity[] = {
312
    0,                                 // No parity
313
    WR4_ParityEn | WR4_ParityEven,     // Even parity
314
    WR4_ParityEn,                      // Odd parity
315
    0xFF,                              // Mark parity
316
    0xFF,                              // Space parity
317
};
318
 
319
static cyg_int32 select_baud[] = {
320
    0,      // Unused
321
    50,     // 50
322
    75,     // 75
323
    110,    // 110
324
    0,      // 134.5
325
    150,    // 150
326
    200,    // 200
327
    300,    // 300
328
    600,    // 600
329
    1200,   // 1200
330
    1800,   // 1800
331
    2400,   // 2400
332
    3600,   // 3600
333
    4800,   // 4800
334
    7200,   // 7200
335
    9600,   // 9600
336
    14400,  // 14400
337
    19200,  // 19200
338
    38400,  // 38400
339
    0,      // 57600
340
    0,      // 115200
341
    0,      // 230400
342
};
343
 
344
#endif // CYGONCE_MIPS_VRC437X_SERIAL_H

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.