1 |
27 |
unneback |
#ifndef CYGONCE_SLEB_SDTR_H
|
2 |
|
|
#define CYGONCE_SLEB_SDTR_H
|
3 |
|
|
//==========================================================================
|
4 |
|
|
//
|
5 |
|
|
// io/serial/sparclite/sleb_sdtr.c
|
6 |
|
|
//
|
7 |
|
|
// Serial I/O interface module for SPARClite Eval Board (SLEB)
|
8 |
|
|
//
|
9 |
|
|
//==========================================================================
|
10 |
|
|
//####ECOSGPLCOPYRIGHTBEGIN####
|
11 |
|
|
// -------------------------------------------
|
12 |
|
|
// This file is part of eCos, the Embedded Configurable Operating System.
|
13 |
|
|
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
|
14 |
|
|
//
|
15 |
|
|
// eCos is free software; you can redistribute it and/or modify it under
|
16 |
|
|
// the terms of the GNU General Public License as published by the Free
|
17 |
|
|
// Software Foundation; either version 2 or (at your option) any later version.
|
18 |
|
|
//
|
19 |
|
|
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
|
20 |
|
|
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
21 |
|
|
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
|
22 |
|
|
// for more details.
|
23 |
|
|
//
|
24 |
|
|
// You should have received a copy of the GNU General Public License along
|
25 |
|
|
// with eCos; if not, write to the Free Software Foundation, Inc.,
|
26 |
|
|
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
|
27 |
|
|
//
|
28 |
|
|
// As a special exception, if other files instantiate templates or use macros
|
29 |
|
|
// or inline functions from this file, or you compile this file and link it
|
30 |
|
|
// with other works to produce a work based on this file, this file does not
|
31 |
|
|
// by itself cause the resulting work to be covered by the GNU General Public
|
32 |
|
|
// License. However the source code for this file must still be made available
|
33 |
|
|
// in accordance with section (3) of the GNU General Public License.
|
34 |
|
|
//
|
35 |
|
|
// This exception does not invalidate any other reasons why a work based on
|
36 |
|
|
// this file might be covered by the GNU General Public License.
|
37 |
|
|
//
|
38 |
|
|
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
|
39 |
|
|
// at http://sources.redhat.com/ecos/ecos-license/
|
40 |
|
|
// -------------------------------------------
|
41 |
|
|
//####ECOSGPLCOPYRIGHTEND####
|
42 |
|
|
//==========================================================================
|
43 |
|
|
//#####DESCRIPTIONBEGIN####
|
44 |
|
|
//
|
45 |
|
|
// Author(s): gthomas
|
46 |
|
|
// Contributors: gthomas
|
47 |
|
|
// Date: 1999-02-04
|
48 |
|
|
// Purpose: SLEB serial I/O module
|
49 |
|
|
// Description:
|
50 |
|
|
//
|
51 |
|
|
//####DESCRIPTIONEND####
|
52 |
|
|
//
|
53 |
|
|
//==========================================================================
|
54 |
|
|
|
55 |
|
|
#include <cyg/hal/hal_io.h> // For I/O macros
|
56 |
|
|
|
57 |
|
|
#define reg(n) ((n)*4)
|
58 |
|
|
|
59 |
|
|
// SDTR Registers
|
60 |
|
|
#define SDTR_TXDATA(base) base+reg(0)
|
61 |
|
|
#define SDTR_RXDATA(base) base+reg(0)
|
62 |
|
|
#define SDTR_STATUS(base) base+reg(1)
|
63 |
|
|
#define SDTR_CONTROL(base) base+reg(1)
|
64 |
|
|
|
65 |
|
|
// Mode register
|
66 |
|
|
#define SDTR_MODE_MODE_MASK 0x03 // Mode selection bits (mask)
|
67 |
|
|
#define SDTR_MODE_MODE_SYNC 0x00 // Synchronous mode
|
68 |
|
|
#define SDTR_MODE_MODE_ASYNC1 0x01 // Async - clock/1
|
69 |
|
|
#define SDTR_MODE_MODE_ASYNC16 0x02 // Async - clock/16
|
70 |
|
|
#define SDTR_MODE_MODE_ASYNC64 0x03 // Async - clock/64
|
71 |
|
|
#define SDTR_MODE_DTB_MASK 0x0C // Number of data bits (mask)
|
72 |
|
|
#define SDTR_MODE_DTB_5 0x00 // 5 bits / char
|
73 |
|
|
#define SDTR_MODE_DTB_6 0x04 // 6 bits / char
|
74 |
|
|
#define SDTR_MODE_DTB_7 0x08 // 7 bits / char
|
75 |
|
|
#define SDTR_MODE_DTB_8 0x0C // 8 bits / char
|
76 |
|
|
#define SDTR_MODE_PARITY_MASK 0x30 // Parity modes (mask)
|
77 |
|
|
#define SDTR_MODE_PARITY_ENABLE 0x10 // Enable parity
|
78 |
|
|
#define SDTR_MODE_PARITY_NONE 0x00 // No parity (parity disabled)
|
79 |
|
|
#define SDTR_MODE_PARITY_ODD 0x00 // Odd parity
|
80 |
|
|
#define SDTR_MODE_PARITY_EVEN 0x20 // Even parity
|
81 |
|
|
#define SDTR_MODE_STOP_BITS_MASK 0xC0 // Number of stop bits (mask)
|
82 |
|
|
#define SDTR_MODE_STOP_BITS_1 0x40 // 1 stop bit
|
83 |
|
|
#define SDTR_MODE_STOP_BITS_1_5 0x80 // 1.5 stop bits
|
84 |
|
|
#define SDTR_MODE_STOP_BITS_2 0xC0 // 2 stop bits
|
85 |
|
|
|
86 |
|
|
// Command register
|
87 |
|
|
#define SDTR_CMD_TxEN 0x01 // Enable transmitter
|
88 |
|
|
#define SDTR_CMD_DTR 0x02 // Assert DTR
|
89 |
|
|
#define SDTR_CMD_RxEN 0x04 // Enable receiver
|
90 |
|
|
#define SDTR_CMD_BREAK 0x08 // Send break
|
91 |
|
|
#define SDTR_CMD_EFR 0x10 // Error flag reset
|
92 |
|
|
#define SDTR_CMD_RTS 0x20 // Assert RTS
|
93 |
|
|
#define SDTR_CMD_RST 0x40 // Internal RESET
|
94 |
|
|
#define SDTR_CMD_EHM 0x80 // Enable Hunt mode
|
95 |
|
|
|
96 |
|
|
// Status register
|
97 |
|
|
#define SDTR_STAT_TxRDY 0x01 // Transmitter ready
|
98 |
|
|
#define SDTR_STAT_RxRDY 0x02 // Receiver ready
|
99 |
|
|
#define SDTR_STAT_TxEMP 0x04 // Transmitter empty
|
100 |
|
|
#define SDTR_STAT_PERR 0x08 // Parity error
|
101 |
|
|
#define SDTR_STAT_OERR 0x10 // Overrun error
|
102 |
|
|
#define SDTR_STAT_FERR 0x20 // Framing error
|
103 |
|
|
#define SDTR_STAT_SYBRK 0x40 // Break
|
104 |
|
|
#define SDTR_STAT_DSR 0x80 // State of DSR signal
|
105 |
|
|
|
106 |
|
|
// Offsets to standard SDTR elements
|
107 |
|
|
#define SLEB_SDTR0_BASE (8*4)
|
108 |
|
|
#define SLEB_SDTR0_TX_INT 9
|
109 |
|
|
#define SLEB_SDTR0_RX_INT 10
|
110 |
|
|
#define SLEB_SDTR1_BASE (12*4)
|
111 |
|
|
#define SLEB_SDTR1_TX_INT 6
|
112 |
|
|
#define SLEB_SDTR1_RX_INT 7
|
113 |
|
|
#define SLEB_TIMER3_CONTROL reg(29)
|
114 |
|
|
#define SLEB_TIMER3_RELOAD reg(30)
|
115 |
|
|
|
116 |
|
|
// On-board switch, used to determine baud rate
|
117 |
|
|
#define SLEB_CLOCK_SWITCH (volatile unsigned char *)0x01000003
|
118 |
|
|
|
119 |
|
|
static unsigned char select_word_length[] = {
|
120 |
|
|
SDTR_MODE_DTB_5, // 5 bits / word (char)
|
121 |
|
|
SDTR_MODE_DTB_6,
|
122 |
|
|
SDTR_MODE_DTB_7,
|
123 |
|
|
SDTR_MODE_DTB_8
|
124 |
|
|
};
|
125 |
|
|
|
126 |
|
|
static unsigned char select_stop_bits[] = {
|
127 |
|
|
0,
|
128 |
|
|
SDTR_MODE_STOP_BITS_1, // 1 stop bit
|
129 |
|
|
SDTR_MODE_STOP_BITS_1_5, // 1.5 stop bit
|
130 |
|
|
SDTR_MODE_STOP_BITS_2 // 2 stop bits
|
131 |
|
|
};
|
132 |
|
|
|
133 |
|
|
static unsigned char select_parity[] = {
|
134 |
|
|
SDTR_MODE_PARITY_NONE, // No parity
|
135 |
|
|
SDTR_MODE_PARITY_ENABLE|SDTR_MODE_PARITY_EVEN, // Even parity
|
136 |
|
|
SDTR_MODE_PARITY_ENABLE|SDTR_MODE_PARITY_ODD, // ODD parity
|
137 |
|
|
0xFF, // Mark parity
|
138 |
|
|
0xFF, // Space parity
|
139 |
|
|
};
|
140 |
|
|
|
141 |
|
|
static cyg_int32 select_baud[] = {
|
142 |
|
|
0, // Unused
|
143 |
|
|
50, // 50
|
144 |
|
|
75, // 75
|
145 |
|
|
110, // 110
|
146 |
|
|
0, // 134.5
|
147 |
|
|
150, // 150
|
148 |
|
|
200, // 200
|
149 |
|
|
300, // 300
|
150 |
|
|
600, // 600
|
151 |
|
|
1200, // 1200
|
152 |
|
|
1800, // 1800
|
153 |
|
|
2400, // 2400
|
154 |
|
|
3600, // 3600
|
155 |
|
|
4800, // 4800
|
156 |
|
|
7200, // 7200
|
157 |
|
|
9600, // 9600
|
158 |
|
|
14400, // 14400
|
159 |
|
|
19200, // 19200
|
160 |
|
|
38400, // 38400
|
161 |
|
|
57600, // 57600
|
162 |
|
|
115200, // 115200
|
163 |
|
|
230400, // 230400
|
164 |
|
|
};
|
165 |
|
|
|
166 |
|
|
#endif // CYGONCE_SLEB_SDTR_H
|
167 |
|
|
|