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//==========================================================================

//

//      usbs_upd985xx.c

//

//      Driver for the NEC uPD985xx USB device

//

//==========================================================================

//####ECOSGPLCOPYRIGHTBEGIN####

// -------------------------------------------

// This file is part of eCos, the Embedded Configurable Operating System.

// Copyright (C) 2002 Bart Veer

// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.

//

// eCos is free software; you can redistribute it and/or modify it under

// the terms of the GNU General Public License as published by the Free

// Software Foundation; either version 2 or (at your option) any later version.

//

// eCos is distributed in the hope that it will be useful, but WITHOUT ANY

// WARRANTY; without even the implied warranty of MERCHANTABILITY or

// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License

// for more details.

//

// You should have received a copy of the GNU General Public License along

// with eCos; if not, write to the Free Software Foundation, Inc.,

// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.

//

// As a special exception, if other files instantiate templates or use macros

// or inline functions from this file, or you compile this file and link it

// with other works to produce a work based on this file, this file does not

// by itself cause the resulting work to be covered by the GNU General Public

// License. However the source code for this file must still be made available

// in accordance with section (3) of the GNU General Public License.

//

// This exception does not invalidate any other reasons why a work based on

// this file might be covered by the GNU General Public License.

//

// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.

// at http://sources.redhat.com/ecos/ecos-license/

// -------------------------------------------

//####ECOSGPLCOPYRIGHTEND####

//==========================================================================

//#####DESCRIPTIONBEGIN####

//

// Author(s):    bartv

// Contributors: bartv

// Date:         2001-05-22

//

// This code implements support for the on-chip USB port on the NEC

// uPD985xx family of processors. The code has been developed on the

// uPD98503 and may or may not work on other members of the uPD985xx

// family.

//

//####DESCRIPTIONEND####

//==========================================================================

#include <cyg/infra/cyg_type.h>

#include <cyg/infra/cyg_ass.h>

#include <cyg/infra/cyg_trac.h>

#include <cyg/infra/diag.h>

#include <pkgconf/hal_mips_upd985xx.h>

#include <pkgconf/devs_usb_upd985xx.h>

#include <cyg/hal/drv_api.h>

#include <cyg/hal/hal_arch.h>

#include <cyg/hal/hal_io.h>

#include <cyg/hal/hal_cache.h>

#include <cyg/error/codes.h>

#include <cyg/io/usb/usb.h>

#include <cyg/io/usb/usbs.h>

// For memcpy()

#include <string.h>

// ----------------------------------------------------------------------------

// Toplevel FIXME's.

//

// The device supports remote wakeups, but this driver does not. Note that

// the device GET_STATUS, SET_FEATURE and CLEAR_FEATURE operations are 

// affected by remote wakeup support.

// ----------------------------------------------------------------------------

// Debugging-related odds and ends.

#if 0

# define DBG(a) diag_printf a

#else

# define DBG(a)

#endif

// ----------------------------------------------------------------------------

// Hardware definitions.

//

// The NEC uPD985Xx on-chip USB device provides the following:

//

// endpoint 0   - control messages only

// endpoint 1   - isochronous transmits

// endpoint 2   - isochronous receives

// endpoint 3   - bulk transmits

// endpoint 4   - bulk receives

// endpoint 5   - interrupt transmits

// endpoint 6   - interrupt receives

// All acess to the USB controller registers goes via the IBUS, which

// always runs little-endian. Hence when the CPU is running

// little-endian no extra work is needed, but when running big-endian

// all register updates involve swapping.

#ifdef CYGPKG_HAL_MIPS_LSBFIRST

# define IBUS_SWAP32(_a_)               (_a_)

# define IBUS_SWAPPTR(_type_, _a_)      (_a_)

#else

# error IBUS_SWAP32() needs to be defined and tested

#endif

// Move an address to kseg1. Or'ing in the relevant bits means

// that this macro will work even if the specified address is

// already in kseg1

#define MIPS_TO_UNCACHED(_a_)  ((void*)(((cyg_uint32)(_a_)) | MIPS_KSEG1_BASE))

// For now access the various registers directly. A structure might

// be marginally more inefficient in that if a function accesses

// several registers this could be handled by a single base plus

// offsets, rather than by separate addresses.

#define USBS_REGISTER(_a_)              ((volatile cyg_uint32*)(MIPS_IO_BASE + UPD985XX_SYSUSB_OFF + (_a_)))

#define USBS_ADDRREG(_type_, _a_)       ((_type_* volatile*)(MIPS_IO_BASE + UPD985XX_SYSUSB_OFF + (_a_)))

#define USBS_GMR                USBS_REGISTER(0x0000)

#define USBS_VER                USBS_REGISTER(0x0004)

#define USBS_GSR1               USBS_REGISTER(0x0010)

#define USBS_IMR1               USBS_REGISTER(0x0014)

#define USBS_GSR2               USBS_REGISTER(0x0018)

#define USBS_IMR2               USBS_REGISTER(0x001C)

#define EP0_CR                  USBS_REGISTER(0x0020)

#define EP1_CR                  USBS_REGISTER(0x0024)

#define EP2_CR                  USBS_REGISTER(0x0028)

#define EP3_CR                  USBS_REGISTER(0x002C)

#define EP4_CR                  USBS_REGISTER(0x0030)

#define EP5_CR                  USBS_REGISTER(0x0034)

#define EP6_CR                  USBS_REGISTER(0x0038)

#define USBS_CMR                USBS_REGISTER(0x0040)

#define USBS_CA                 USBS_ADDRREG(void, 0x0044)

#define USBS_TEPSR              USBS_REGISTER(0x0048)

#define USBS_RP0IR              USBS_REGISTER(0x0050)

#define USBS_RP0AR              USBS_ADDRREG(RxBufferDescriptor, 0x0054)

#define USBS_RP1IR              USBS_REGISTER(0x0058)

#define USBS_RP1AR              USBS_ADDRREG(RxBufferDescriptor, 0x005C)

#define USBS_RP2IR              USBS_REGISTER(0x0060)

#define USBS_RP2AR              USBS_ADDRREG(RxBufferDescriptor, 0x0064)

#define USBS_TMSA               USBS_ADDRREG(TxMailbox, 0x0070)

#define USBS_TMBA               USBS_ADDRREG(TxMailbox, 0x0074)

#define USBS_TMRA               USBS_ADDRREG(TxMailbox, 0x0078)

#define USBS_TMWA               USBS_ADDRREG(TxMailbox, 0x007C)

#define USBS_RMSA               USBS_ADDRREG(RxMailbox, 0x0080)

#define USBS_RMBA               USBS_ADDRREG(RxMailbox, 0x0084)

#define USBS_RMRA               USBS_ADDRREG(RxMailbox, 0x0088)

#define USBS_RMWA               USBS_ADDRREG(RxMailbox, 0x008C)

// There are additional counter registers from offset 0x100 onwards.

// These registers are not used by the driver, and anyway may not be

// available on all hardware.

// The General Mode register USBS_GMR

#define USBS_GMR_VT                     (0x01 << 23)

#define USBS_GMR_FA_MASK                (0x7F << 16)

#define USBS_GMR_FA_SHIFT               16

#define USBS_GMR_SOFINTVL_MASK          (0x00FF << 8)

#define USBS_GMR_SOFINTVL_SHIFT         8

#define USBS_GMR_SOFINTVL_DEFAULT_VALUE (0x18 << 8)

#define USBS_GMR_AU                     (0x01 << 2)

#define USBS_GMR_LE                     (0x01 << 1)

#define USBS_GMR_RR                     (0x01 << 0)

// The Frame Number/Version register

#define USBS_VER_UVER_MASK              (0x0FFFF << 16)

#define USBS_VER_UVER_SHIFT             16

#define USBS_VER_UFNR_MASK              (0x03FF << 0)

#define USBS_VER_UFNR_SHIFT             0

// General status register 1

#define USBS_GSR1_GSR2                  (0x01 << 31)

#define USBS_GSR1_TMF                   (0x01 << 23)

#define USBS_GSR1_RMF                   (0x01 << 22)

#define USBS_GSR1_RPE2                  (0x01 << 21)

#define USBS_GSR1_RPE1                  (0x01 << 20)

#define USBS_GSR1_RPE0                  (0x01 << 19)

#define USBS_GSR1_RPA2                  (0x01 << 18)

#define USBS_GSR1_RPA1                  (0x01 << 17)

#define USBS_GSR1_RPA0                  (0x01 << 16)

#define USBS_GSR1_DER                   (0x01 << 10)

#define USBS_GSR1_EP2FO                 (0x01 << 9)

#define USBS_GSR1_EP1FU                 (0x01 << 8)

#define USBS_GSR1_EP6RF                 (0x01 << 7)

#define USBS_GSR1_EP5TF                 (0x01 << 6)

#define USBS_GSR1_EP4RF                 (0x01 << 5)

#define USBS_GSR1_EP3TF                 (0x01 << 4)

#define USBS_GSR1_EP2RF                 (0x01 << 3)

#define USBS_GSR1_EP1TF                 (0x01 << 2)

#define USBS_GSR1_EP0RF                 (0x01 << 1)

#define USBS_GSR1_EP0TF                 (0x01 << 0)

// The Interrupt mask 1 bits correspond to the GSR1 bits above

// General status register 2

#define USBS_GSR2_FW                    (0x01 << 21)

#define USBS_GSR2_IFN                   (0x01 << 20)

#define USBS_GSR2_IEA                   (0x01 << 19)

#define USBS_GSR2_URSM                  (0x01 << 18)

#define USBS_GSR2_URST                  (0x01 << 17)

#define USBS_GSR2_USPD                  (0x01 << 16)

#define USBS_GSR2_EP2OS                 (0x01 << 7)

#define USBS_GSR2_EP2ED                 (0x01 << 6)

#define USBS_GSR2_EP2ND                 (0x01 << 5)

#define USBS_GSR2_EP1NT                 (0x01 << 4)

#define USBS_GSR2_EP1ET                 (0x01 << 3)

#define USBS_GSR2_EP1ND                 (0x01 << 2)

#define USBS_GSR2_ES                    (0x01 << 1)

#define USBS_GSR2_SL                    (0x01 << 0)

// Interrupt mask 2 bits correspond to GSR2

// Endpoint control registers.

// EP0 - control messages

#define EP0_CR_EP0EN                    (0x01 << 31)

#define EP0_CR_ISS                      (0x01 << 20)

#define EP0_CR_INAK                     (0x01 << 19)

#define EP0_CR_OSS                      (0x01 << 18)

#define EP0_CR_NHSK0                    (0x01 << 17)

#define EP0_CR_ONAK                     (0x01 << 16)

#define EP0_CR_MAXP0_MASK               (0x7F << 0)

#define EP0_CR_MAXP0_SHIFT              0

// EP1 - isochronous transmits

#define EP1_CR_EP1EN                    (0x01 << 31)

#define EP1_CR_TM1                      (0x01 << 19)

#define EP1_CR_TM1_MASK                 (0x01 << 19)

#define EP1_CR_TM1_SZLP                 (0x00 << 19)

#define EP1_CR_TM1_NZLP                 (0x01 << 19)

#define EP1_CR_MAXP1_MASK               (0x3FF << 0)

#define EP1_CR_MAXP1_SHIFT              0

// EP2 - isochronous receives

#define EP2_CR_EP2EN                    (0x01 << 31)

#define EP2_CR_RM2_MASK                 (0x03 << 19)

#define EP2_CR_RM2_NORMAL               (0x00 << 19)

#define EP2_CR_RM2_ASSEMBLE             (0x02 << 19)

#define EP2_CR_RM2_SEPARATE             (0x03 << 19)

#define EP2_CR_MAXP2_MASK               (0x3FF << 0)

#define EP2_CR_MAXP2_SHIFT              0

// EP3 - bulk transmits

#define EP3_CR_EP3EN                    (0x01 << 31)

#define EP3_CR_TM3                      (0x01 << 19)

#define EP3_CR_TM3_MASK                 (0x01 << 19)

#define EP3_CR_TM3_SZLP                 (0x00 << 19)

#define EP3_CR_TM3_NZLP                 (0x01 << 19)

#define EP3_CR_SS3                      (0x01 << 18)

#define EP3_CR_NAK3                     (0x01 << 16)

#define EP3_CR_MAXP3_MASK               (0x7F << 0)

#define EP3_CR_MAXP3_SHIFT              0

// EP4 - bulk receives

#define EP4_CR_EP4EN                    (0x01 << 31)

#define EP4_CR_RM4_MASK                 (0x03 << 19)

#define EP4_CR_RM4_NORMAL               (0x00 << 19)

#define EP4_CR_RM4_ASSEMBLE             (0x02 << 19)

#define EP4_CR_RM4_SEPARATE             (0x03 << 19)

#define EP4_CR_SS4                      (0x01 << 18)

#define EP4_CR_NHSK4                    (0x01 << 17)

#define EP4_CR_NAK4                     (0x01 << 16)

#define EP4_CR_MAXP4_MASK               (0x7F << 0)

#define EP4_CR_MAXP4_SHIFT              0

// EP5 - interrupt transmits

#define EP5_CR_EP5EN                    (0x01 << 31)

#define EP5_CR_FM                       (0x01 << 19)

#define EP5_CR_SS5                      (0x01 << 18)

#define EP5_CR_NAK5                     (0x01 << 16)

#define EP5_CR_MAXP5_MASK               (0x7F << 0)

#define EP5_CR_MAXP5_SHIFT              0

// EP6 - interrupt receives

#define EP6_CR_EP6EN                    (0x01 << 31)

#define EP6_CR_SS6                      (0x01 << 18)

#define EP6_CR_NHSK6                    (0x01 << 17)

#define EP6_CR_NAK6                     (0x01 << 16)

#define EP6_CR_MAXP6_MASK               (0x7F << 0)

#define EP6_CR_MAXP6_SHIFT              0

// Some bits which can be applied to multiple transmit or receive

// endpoint control registers, thus avoiding unnecessary code

// duplication. These will not work for the isochronous endpoints

// because those are just too special.

#define EPtx_CR_EpxEN                   (0x01 << 31)

#define EPtx_CR_SSx                     (0x01 << 18)

#define EPtx_CR_NAKx                    (0x01 << 16)

#define EPtx_CR_MAXPx_MASK              (0x7F << 0)

#define EPtx_CR_MAXPx_SHIFT             0

#define EPrx_CR_EPxEN                   (0x01 << 31)

#define EPrx_CR_SSx                     (0x01 << 18)

#define EPrx_CR_NHSKx                   (0x01 << 17)

#define EPrx_CR_NAKx                    (0x01 << 16)

#define EPrx_CR_MAXPx_MASK              (0x7F << 0)

#define EPrx_CR_MAXPx_SHIFT             0

// USB command register

#define USBS_CMR_BUSY                   (0x01 << 31)

#define USBS_CMR_COMMAND_MASK           (0x07 << 24)

#define USBS_CMR_COMMAND_SHIFT          24

#define USBS_CMR_COMMAND_TX_EP0         (0x00 << 24)

#define USBS_CMR_COMMAND_TX_EP1         (0x01 << 24)

#define USBS_CMR_COMMAND_TX_EP3         (0x02 << 24)

#define USBS_CMR_COMMAND_TX_EP5         (0x03 << 24)

#define USBS_CMR_COMMAND_ADD_POOL0      (0x04 << 24)

#define USBS_CMR_COMMAND_ADD_POOL1      (0x05 << 24)

#define USBS_CMR_COMMAND_ADD_POOL2      (0x06 << 24)

#define USBS_CMR_SIZE_MASK              (0x0FFFF << 0)

#define USBS_CMR_SIZE_SHIFT             0

// TX Endpoint status

#define USBS_TEPSR_EP5TS_MASK           (0x03 << 24)

#define USBS_TEPSR_EP5TS_SHIFT          24

#define USBS_TEPSR_EP5TS_IDLE           (0x00 << 24)

#define USBS_TEPSR_EP5TS_ONE            (0x01 << 24)

#define USBS_TEPSR_EP5TS_TWO            (0x02 << 24)

#define USBS_TEPSR_EP3TS_MASK           (0x03 << 16)

#define USBS_TEPSR_EP3TS_SHIFT          16

#define USBS_TEPSR_EP3TS_IDLE           (0x00 << 16)

#define USBS_TEPSR_EP3TS_ONE            (0x01 << 16)

#define USBS_TEPSR_EP3TS_TWO            (0x02 << 16)

#define USBS_TEPSR_EP1TS_MASK           (0x03 << 8)

#define USBS_TEPSR_EP1TS_SHIFT          8

#define USBS_TEPSR_EP1TS_IDLE           (0x00 << 8)

#define USBS_TEPSR_EP1TS_ONE            (0x01 << 8)

#define USBS_TEPSR_EP1TS_TWO            (0x02 << 8)

#define USBS_TEPSR_EP0TS_MASK           (0x03 << 0)

#define USBS_TEPSR_EP0TS_SHIFT          0

#define USBS_TEPSR_EP0TS_IDLE           (0x00 << 0)

#define USBS_TEPSR_EP0TS_ONE            (0x01 << 0)

#define USBS_TEPSR_EP0TS_TWO            (0x02 << 0)

// Receive pools. The RP0IR, RP1IR and RP2IR registers

// all use the same bits.

#define USBS_RPxIR_AL_MASK              (0x07 << 28)

#define USBS_RPxIR_AL_SHIFT             28

#define USBS_RPxIR_AL_NONE              (0 << 28)

#define USBS_RPxIR_RNOD_MASK            (0x0FFFF << 0)

#define USBS_RPxIR_RNOD_SHIFT           0

// The other registers do not have special bits.

// Data transfers involve buffer descriptors and mailboxes. The

// relevant data structures and fields need to be defined. For now

// assume 32-bit mode of operation, i.e. there will be no padding

// between two successive 32-bit entities

// A transmit packet directory consists of up to 255 buffer

// descriptors. Each buffer descriptor specifies a buffer and a size

// of up to 64K. 

typedef struct TxBufferDescriptor {

    cyg_uint32  control;

    void*       buffer;

} TxBufferDescriptor;

#define TXBUFDESC_CTRL_LAST                     (0x01 << 31)

#define TXBUFDESC_CTRL_BUFDESC_MASK             (0x01 << 30)

#define TXBUFDESC_CTRL_BUFDESC_SHIFT            30

#define TXBUFDESC_CTRL_BUFDESC_LINK             (0x00 << 30)

#define TXBUFDESC_CTRL_BUFDESC_BUFDESC          (0x01 << 30)

#define TXBUFDESC_CTRL_SIZE_MASK                (0x0FFFF << 0)

#define TXBUFDESC_CTRL_SIZE_SHIFT               0

// The result of a transmit operation gets written to a mailbox

// structure in memory.

typedef struct TxMailbox {

    cyg_uint32  status;

} TxMailbox;

#define TXMBOX_STATUS_IBUS_ERROR                (0x01 << 10)

#define TXMBOX_STATUS_UNDERRUN                  (0x01 << 9)

#define TXMBOX_STATUS_MODE_MASK                 (0x01 << 8)

#define TXMBOX_STATUS_MODE_SHIFT                8

#define TXMBOX_STATUS_MODE_SZLP                 (0x00 << 8)

#define TXMBOX_STATUS_MODE_NZLP                 (0x01 << 8)

#define TXMBOX_STATUS_EPN_MASK                  (0x07 << 0)

#define TXMBOX_STATUS_EPN_SHIFT                 0

#define TXMBOX_STATUS_EPN_EP0                   (0x00 << 0)

#define TXMBOX_STATUS_EPN_EP1                   (0x02 << 0)

#define TXMBOX_STATUS_EPN_EP3                   (0x04 << 0)

#define TXMBOX_STATUS_EPN_EP5                   (0x06 << 0)

// Now for receive operations. This involves adding buffer descriptors

// to one of three pools. The pools are managed by registers.

typedef struct RxBufferDescriptor {

    cyg_uint32          control;

    void*               buffer;

} RxBufferDescriptor;

#define RXBUFDESC_CTRL_LAST                     (0x01 << 31)

#define RXBUFDESC_CTRL_BUFDESC_MASK             (0x01 << 30)

#define RXBUFDESC_CTRL_BUFDESC_SHIFT            30

#define RXBUFDESC_CTRL_BUFDESC_LINK             (0x00 << 30)

#define RXBUFDESC_CTRL_BUFDESC_BUFDESC          (0x01 << 30)

#define RXBUFDESC_CTRL_SIZE_MASK                (0x0FFFF << 0)

#define RXBUFDESC_CTRL_SIZE_SHIFT               0

typedef struct RxMailbox {

    cyg_uint32          status;

    void*               address;

} RxMailbox;

#define RXMBOX_STATUS_EPN_MASK                  (0x07 << 29)

#define RXMBOX_STATUS_EPN_SHIFT                 29

#define RXMBOX_STATUS_EPN_EP0                   (0x01 << 29)

#define RXMBOX_STATUS_EPN_EP2                   (0x03 << 29)

#define RXMBOX_STATUS_EPN_EP4                   (0x05 << 29)

#define RXMBOX_STATUS_EPN_EP6                   (0x07 << 29)

#define RXMBOX_STATUS_CORRUPTION                (0x01 << 25)

#define RXMBOX_STATUS_IBUS_ERROR                (0x01 << 24)

#define RXMBOX_STATUS_SETUP_MASK                (0x01 << 23)

#define RXMBOX_STATUS_SETUP_SHIFT               23

#define RXMBOX_STATUS_SETUP_NORMAL              (0x00 << 23)

#define RXMBOX_STATUS_SETUP_SETUP               (0x01 << 23)

#define RXMBOX_STATUS_OVERRUN                   (0x01 << 22)

#define RXMBOX_STATUS_DATA_TOGGLE               (0x01 << 21)

#define RXMBOX_STATUS_CRC                       (0x01 << 20)

#define RXMBOX_STATUS_BIT_STUFFING              (0x01 << 19)

#define RXMBOX_STATUS_64K                       (0x01 << 18)

#define RXMBOX_STATUS_MODE_MASK                 (0x03 << 16)

#define RXMBOX_STATUS_MODE_SHIFT                16

#define RXMBOX_STATUS_MODE_NORMAL               (0x00 << 16)

#define RXMBOX_STATUS_MODE_NORMAL2              (0x01 << 16)

#define RXMBOX_STATUS_MODE_ASSEMBLE             (0x02 << 16)

#define RXMBOX_STATUS_MODE_SEPARATE             (0x03 << 16)

#define RXMBOX_STATUS_SIZE_MASK                 (0x0FFFF << 0)

#define RXMBOX_STATUS_SIZE_SHIFT                0

// ----------------------------------------------------------------------------

// Hardware work around - see NEC erratum S1, CPU to IBUS write restriction.

// Reading back from the USB device after every write prevents any problems.

// Strictly speaking it is only necessary to do this after every three

// writes, but if there is concurrent ethernet activity then doing it

// after eveyr write is safer. The frame number/version register seems

// like a good one to read back from.

#ifdef CYGIMP_DEVS_USB_UPD985XX_IBUS_WRITE_LIMIT

# define FLUSH_IBUS()   \

      CYG_MACRO_START   \

      (void)*USBS_VER;  \

      CYG_MACRO_END

#else

# define FLUSH_IBUS()       CYG_EMPTY_STATEMENT

#endif

// ----------------------------------------------------------------------------

// Static data. There is a data structure for each endpoint. The

// implementation is essentially a private class that inherits from

// common classes for control and data endpoints, but device drivers

// are supposed to be written in C so some ugliness is required.

//

// Devtab entries are defined in usbs_upd985xx_data.cxx to make sure

// that the linker does not garbage-collect them.

// Support for the interrupt handling code.

static cyg_interrupt usbs_upd985xx_intr_data;

static cyg_handle_t  usbs_upd985xx_intr_handle;

// The various bits in the two interrupt status registers are read-once,

// i.e. reading the register clears the bits. Since much of the processing

// is deferred to DSR level, it is necessary to keep track of pending

// interrupts in separate variables. If another interrupt happens during

// DSR processing, these variables will be updated. The main DSR loops

// until there are no interesting bits left. Interrupts have to be

// disabled briefly when clearing bits.

static volatile cyg_uint32 usbs_upd985xx_gsr1   = 0;

static volatile cyg_uint32 usbs_upd985xx_gsr2   = 0;

// Many of the interrupt bits are of no interest and it is convenient

// to mask them out in the ISR, thus avoiding unnecessary dsr

// invocations.

static cyg_uint32 usbs_upd985xx_gsr1_mask       = 0;

static cyg_uint32 usbs_upd985xx_gsr2_mask       = 0;

// Sizes for the receive and transmit mboxes.

// NOTE: it is not clear what the optimal size for these

// mailboxes is. For receives maybe one per rx endpoint,

// plus a spare. For transmits maybe just two, since only

// one transmit at a time is supported. Mailboxes are

// relatively small, so for now four each should be ok.

#define RXMBOX_COUNT    4

#define TXMBOX_COUNT    4

// There is one instance of this data structure. It is allocated

// in kseg0 cached memory, but during initialization a separate

// pointer value is set to the kseg1 uncached equivalent. This

// makes it easier to point the hardware at uncached memory without

// having to worry about cache line boundaries everywhere.

typedef struct uncached_data {

    // This partial cacheline does not actually store any data.

    // However it ensures that the data does not share a cacheline

    // with some other static, with updates to that other static

    // causing funny side effects on the uncached data. There is a

    // memory optimisation of subtracting sizeof(RxMailbox.status),

    // i.e. exploit knowledge of alignment.

    unsigned char       cacheline_start[HAL_DCACHE_LINE_SIZE - sizeof(cyg_uint32)];

    RxMailbox           rx_mboxes[RXMBOX_COUNT];

    TxMailbox           tx_mboxes[TXMBOX_COUNT];

    // For transmits a single buffer descriptor per endpoint suffices.

    // If transmit locking is enabled then actually a single buffer

    // descriptor for the whole system would suffice.

    TxBufferDescriptor  ep0_tx_bufdesc;

#ifdef CYGPKG_DEVS_USB_UPD985XX_EP3

    TxBufferDescriptor  ep3_tx_bufdesc;

#endif

#ifdef CYGPKG_DEVS_USB_UPD985XX_EP5

    TxBufferDescriptor  ep5_tx_bufdesc;

#endif

    // More buffer descriptors are needed than might be expected, see

    // the start_rx routines. 

    RxBufferDescriptor  ep0_rx_bufdescs[4];

#ifdef CYGPKG_DEVS_USB_UPD985XX_EP4

    RxBufferDescriptor  ep4_rx_bufdescs[8];

#endif    

#ifdef CYGPKG_DEVS_USB_UPD985XX_EP4

    // Space for the start and end of a transfer, avoiding problems

    // with invalidating partial cache lines.

    unsigned char       ep4_head[HAL_DCACHE_LINE_SIZE];

    unsigned char       ep4_tail[HAL_DCACHE_LINE_SIZE];

#endif

    // The "big" buffers come last, reducing the offsets for the previous

    // structures. It is not clear this really matters for MIPS.

    //

    // Endpoint 0 receive and transmit buffers. A transmit buffer is

    // convenient because the hardware pretty much expects all of the

    // data to be in contiguous memory, as opposed to the normal eCos

    // USB driver model with refill buffers etc. An alternative

    // implementation would keep the data in separate areas but would

    // require lots of TxBufferDescriptors, so in memory terms the

    // overheads of a single transmit buffer are not as big as might

    // seem. It might be possible to get things working eight bytes

    // at a time since the hardware appears to depend on zero-byte

    // terminating packets in places, but that has not been attempted.

    //

    // A separate receive buffer is useful because it can be placed in

    // uncached memory, avoiding the need for invalidation and

    // worrying about other data in the cache lines. Note that this

    // buffer may also get used for endpoint 6 interrupt receives

    // because the two endpoints share a single pool.

    unsigned char       ep0_rx_buffer[CYGNUM_DEVS_USB_UPD985XX_EP0_RXBUFSIZE];

    unsigned char       ep0_tx_buffer[CYGNUM_DEVS_USB_UPD985XX_EP0_TXBUFSIZE];

    // Another cacheline to prevent overlap with other statics.

    // This has to be full-sized since the previous field is only byte-aligned.

    unsigned char       cacheline_end[HAL_DCACHE_LINE_SIZE];

} uncached_data;

// This data structure is quite large so making it all uninitialized

// means a potentially big saving in ROM-booting systems. This

// requires additional effort by the endpoint initialization routines.

static uncached_data    cached_copy;

static uncached_data*   uncached        = (uncached_data*)0;

// Endpoint 0. See the description below.

static void usbs_upd985xx_ep0_start(usbs_control_endpoint*);

static void usbs_upd985xx_poll(usbs_control_endpoint*);

typedef struct ep0_impl {

    usbs_control_endpoint       common;

    cyg_bool                    rx_expecting_data;

    cyg_bool                    rx_indicator_valid;

    RxMailbox                   rx_indicator;

    cyg_bool                    tx_indicator_valid;

    TxMailbox                   tx_indicator;

    cyg_bool                    tx_needs_zero_transfer;

    cyg_uint32                  tx_size;

} ep0_impl;

static ep0_impl ep0 = {

    common:

    {

        state:                  USBS_STATE_POWERED, // The hardware does not distinguish  between detached, attached and powered.

        enumeration_data:       (usbs_enumeration_data*) 0,

        start_fn:               &usbs_upd985xx_ep0_start,

        poll_fn:                &usbs_upd985xx_poll,

        interrupt_vector:       CYGNUM_HAL_INTERRUPT_USB,

        control_buffer:         { 0, 0, 0, 0, 0, 0, 0, 0 },

        state_change_fn:        (void (*)(usbs_control_endpoint*, void*, usbs_state_change, int)) 0,

        state_change_data:      (void*) 0,

        standard_control_fn:    (usbs_control_return (*)(usbs_control_endpoint*, void*)) 0,

        standard_control_data:  (void*) 0,

        class_control_fn:       (usbs_control_return (*)(usbs_control_endpoint*, void*)) 0,

        class_control_data:     (void*) 0,

        vendor_control_fn:      (usbs_control_return (*)(usbs_control_endpoint*, void*)) 0,

        vendor_control_data:    (void*) 0,

        reserved_control_fn:    (usbs_control_return (*)(usbs_control_endpoint*, void*)) 0,

        reserved_control_data:  (void*) 0,

        buffer:                 (unsigned char*) 0,

        buffer_size:            0,

        fill_buffer_fn:         (void (*)(usbs_control_endpoint*)) 0,

        fill_data:              (void*) 0,

        fill_index:             0,

        complete_fn:            (usbs_control_return (*)(usbs_control_endpoint*, int)) 0

    },

    rx_expecting_data:          false,

    rx_indicator_valid:         false,

    rx_indicator:               { 0, (void*) 0 },

    tx_indicator_valid:         false,

    tx_indicator:               { 0 },

    tx_needs_zero_transfer:     0

};

extern usbs_control_endpoint usbs_upd985xx_ep0 __attribute__((alias ("ep0")));

// Endpoint 1, isochronous transmits. This endpoint is not yet

// supported. Although the interface for bulk transmits should be

// mostly re-usable, there are some additional error conditions if

// either the host or the target fails to achieve the desired

// throughput.

// Endpoint 2, isochronous receives. Not yet supported for now, just

// like endpoint 1.

// Endpoints 3 and 5 can share some code.

#if defined(CYGPKG_DEVS_USB_UPD985XX_EP3) || defined(CYGPKG_DEVS_USB_UPD985XX_EP5)

// Endpoint 3, bulk transmits, and endpoint 5, either interrupt transmits

// or emulation of bulk transmits. The hardware does most

// of the work.

typedef struct ep35_impl {

    usbs_tx_endpoint        common;

    cyg_bool                tx_indicator_valid;

    TxMailbox               tx_indicator;

    int                     send_command;

    volatile cyg_uint32*    cr;

    TxBufferDescriptor*     tx_bufdesc;

} ep35_impl;

# ifdef CYGPKG_DEVS_USB_UPD985XX_EP3

static void ep3_start_tx(usbs_tx_endpoint*);

static void ep3_set_halted(usbs_tx_endpoint*, cyg_bool);

static ep35_impl ep3 = {

    common: {

        start_tx_fn:        &ep3_start_tx,

        set_halted_fn:      &ep3_set_halted,

        complete_fn:        (void (*)(void*, int)) 0,

        complete_data:      (void*) 0,

        buffer:             (const unsigned char*) 0,

        buffer_size:        0,

        halted:             0,

    },

    tx_indicator_valid: false,

    tx_indicator:       { 0 },

    send_command:       USBS_CMR_COMMAND_TX_EP3,

    cr:                 EP3_CR,

    tx_bufdesc:         0       // Needs run-time initialization

};

extern usbs_tx_endpoint usbs_upd985xx_ep3 __attribute__ ((alias ("ep3")));

# endif

# ifdef CYGPKG_DEVS_USB_UPD985XX_EP5

static void ep5_start_tx(usbs_tx_endpoint*);

static void ep5_set_halted(usbs_tx_endpoint*, cyg_bool);

static ep35_impl ep5 = {

    common: {

        start_tx_fn:        &ep5_start_tx,

        set_halted_fn:      &ep5_set_halted,

        complete_fn:        (void (*)(void*, int)) 0,

        complete_data:      (void*) 0,

        buffer:             (const unsigned char*) 0,

        buffer_size:        0,

        halted:             0,

    },

    tx_indicator_valid: false,

    tx_indicator:       { 0 },

    send_command:       USBS_CMR_COMMAND_TX_EP5,

    cr:                 EP5_CR,

    tx_bufdesc:         0       // Needs run-time initialization

};

extern usbs_tx_endpoint usbs_upd985xx_ep5 __attribute__ ((alias ("ep5")));

# endif

#endif

#ifdef CYGPKG_DEVS_USB_UPD985XX_EP4

// Endpoint 4, bulk receives. Again the hardware does the hard work.

// Receive pool 2 is reserved for this endpoint.

typedef struct ep4_impl {

    usbs_rx_endpoint    common;

    cyg_uint32          head_size;

    cyg_uint32          direct_size;

    cyg_uint32          tail_size;

    cyg_bool            rx_indicator_valid;

    RxMailbox           rx_indicator;

    cyg_int32           tail_index;

} ep4_impl;

static void ep4_start_rx(usbs_rx_endpoint*);

static void ep4_set_halted(usbs_rx_endpoint*, cyg_bool);

static ep4_impl ep4 = {

    common: {

        start_rx_fn:        &ep4_start_rx,

        set_halted_fn:      &ep4_set_halted,

        complete_fn:        (void (*)(void*, int)) 0,

        complete_data:      (void*) 0,

        buffer:             (unsigned char*) 0,

        buffer_size:        0,

        halted:             0,

    },

    rx_indicator_valid:     false,

    rx_indicator:           { 0, (void*) 0 },

    tail_index:             -1

};

extern usbs_rx_endpoint usbs_upd985xx_ep4 __attribute__((alias ("ep4")));

#endif

// Endpoint 6, interrupt receives. Not yet implemented. There may

// be conflicts because the hardware is shared with endpoint 0.

// ----------------------------------------------------------------------------

// Mailbox support.

//

// The transmit and receive mailboxes are shared between the

// appropriate endpoints. This causes some complications if e.g.

// transmits on several endpoints complete at the same time. For

// example the tx mailbox might contain send indicators for endpoints

// 3 and 0, but the DSR code will process endpoint 0 before endpoint

// 3.

//

// This device driver works on the basis that there can be only one

// transmit and/or receive in progress for any given endpoint, so the

// relevant information can be extracted from the mailbox and put into

// the per-endpoint structures. The routines below can be used to

// move data from the mailboxes. They will be called in DSR context

// so there is no need to worry about locking.

static void

drain_tx_mailbox(void)

{

    TxMailbox*  tmra    = IBUS_SWAPPTR(TxMailbox, *USBS_TMRA);

    TxMailbox*  tmwa    = IBUS_SWAPPTR(TxMailbox, *USBS_TMWA);

    if (tmra != tmwa) {

        do {

            TxMailbox mbox = *tmra;

            tmra++;

            if (tmra == &(uncached->tx_mboxes[TXMBOX_COUNT])) {