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#ifndef CYGONCE_HAL_INTR_H
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#define CYGONCE_HAL_INTR_H
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//==========================================================================
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//
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// hal_intr.h
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//
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// HAL Interrupt and clock support
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//
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//==========================================================================
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//####ECOSGPLCOPYRIGHTBEGIN####
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// -------------------------------------------
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// This file is part of eCos, the Embedded Configurable Operating System.
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// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
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//
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// eCos is free software; you can redistribute it and/or modify it under
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// the terms of the GNU General Public License as published by the Free
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// Software Foundation; either version 2 or (at your option) any later version.
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//
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// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// for more details.
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//
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// You should have received a copy of the GNU General Public License along
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// with eCos; if not, write to the Free Software Foundation, Inc.,
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// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
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//
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// As a special exception, if other files instantiate templates or use macros
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// or inline functions from this file, or you compile this file and link it
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// with other works to produce a work based on this file, this file does not
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// by itself cause the resulting work to be covered by the GNU General Public
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// License. However the source code for this file must still be made available
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// in accordance with section (3) of the GNU General Public License.
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//
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// This exception does not invalidate any other reasons why a work based on
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// this file might be covered by the GNU General Public License.
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//
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// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
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// at http://sources.redhat.com/ecos/ecos-license/
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// -------------------------------------------
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//####ECOSGPLCOPYRIGHTEND####
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//==========================================================================
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//#####DESCRIPTIONBEGIN####
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//
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// Author(s): nickg, gthomas
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// Contributors: nickg, gthomas,
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// jlarmour
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// Date: 1999-02-20
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// Purpose: Define Interrupt support
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// Description: The macros defined here provide the HAL APIs for handling
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// interrupts and the clock.
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//
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// Usage: #include <cyg/hal/hal_intr.h>
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// ...
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//
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//
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//####DESCRIPTIONEND####
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//
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//==========================================================================
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#include <pkgconf/hal.h>
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#include <cyg/infra/cyg_type.h>
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// This is to allow a variant to decide that there is no platform-specific
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// interrupts file; and that in turn can be overridden by a platform that
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// refines the variant's ideas.
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#ifdef CYGBLD_HAL_PLF_INTS_H
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# include CYGBLD_HAL_PLF_INTS_H // should include variant data as required
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#else
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# ifdef CYGBLD_HAL_VAR_INTS_H
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# include CYGBLD_HAL_VAR_INTS_H
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# else
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# include <cyg/hal/hal_platform_ints.h> // default less-complex platforms
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# endif
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#endif
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// Spurious interrupt (no interrupt source could be found)
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#define CYGNUM_HAL_INTERRUPT_NONE -1
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//--------------------------------------------------------------------------
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// ARM exception vectors.
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// These vectors correspond to VSRs. These values are the ones to use for
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// HAL_VSR_GET/SET
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#define CYGNUM_HAL_VECTOR_RESET 0
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#define CYGNUM_HAL_VECTOR_UNDEF_INSTRUCTION 1
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#define CYGNUM_HAL_VECTOR_SOFTWARE_INTERRUPT 2
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#define CYGNUM_HAL_VECTOR_ABORT_PREFETCH 3
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#define CYGNUM_HAL_VECTOR_ABORT_DATA 4
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#define CYGNUM_HAL_VECTOR_reserved 5
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#define CYGNUM_HAL_VECTOR_IRQ 6
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#define CYGNUM_HAL_VECTOR_FIQ 7
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#define CYGNUM_HAL_VSR_MIN 0
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#define CYGNUM_HAL_VSR_MAX 7
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#define CYGNUM_HAL_VSR_COUNT 8
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// Exception vectors. These are the values used when passed out to an
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// external exception handler using cyg_hal_deliver_exception()
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#define CYGNUM_HAL_EXCEPTION_ILLEGAL_INSTRUCTION \
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CYGNUM_HAL_VECTOR_UNDEF_INSTRUCTION
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#define CYGNUM_HAL_EXCEPTION_INTERRUPT \
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CYGNUM_HAL_VECTOR_SOFTWARE_INTERRUPT
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#define CYGNUM_HAL_EXCEPTION_CODE_ACCESS CYGNUM_HAL_VECTOR_ABORT_PREFETCH
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#define CYGNUM_HAL_EXCEPTION_DATA_ACCESS CYGNUM_HAL_VECTOR_ABORT_DATA
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#define CYGNUM_HAL_EXCEPTION_MIN CYGNUM_HAL_EXCEPTION_ILLEGAL_INSTRUCTION
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#define CYGNUM_HAL_EXCEPTION_MAX CYGNUM_HAL_EXCEPTION_DATA_ACCESS
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#define CYGNUM_HAL_EXCEPTION_COUNT (CYGNUM_HAL_EXCEPTION_MAX - \
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CYGNUM_HAL_EXCEPTION_MIN + 1)
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//--------------------------------------------------------------------------
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// Static data used by HAL
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// ISR tables
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externC CYG_ADDRESS hal_interrupt_handlers[CYGNUM_HAL_ISR_COUNT];
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externC CYG_ADDRWORD hal_interrupt_data[CYGNUM_HAL_ISR_COUNT];
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externC CYG_ADDRESS hal_interrupt_objects[CYGNUM_HAL_ISR_COUNT];
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// VSR table
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externC CYG_ADDRESS hal_vsr_table[CYGNUM_HAL_VSR_COUNT];
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// Platform setup memory size (0 if unknown by hardware)
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externC CYG_ADDRWORD hal_dram_size;
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// what, if anything, this means, is platform dependent:
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externC CYG_ADDRWORD hal_dram_type;
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#if CYGINT_HAL_ARM_MEM_REAL_REGION_TOP
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externC cyg_uint8 *hal_arm_mem_real_region_top( cyg_uint8 *_regionend_ );
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# define HAL_MEM_REAL_REGION_TOP( _regionend_ ) \
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hal_arm_mem_real_region_top( _regionend_ )
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#endif
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//--------------------------------------------------------------------------
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// Default ISR
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// The #define is used to test whether this routine exists, and to allow
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// code outside the HAL to call it.
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externC cyg_uint32 hal_default_isr(CYG_ADDRWORD vector, CYG_ADDRWORD data);
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#define HAL_DEFAULT_ISR hal_default_isr
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//--------------------------------------------------------------------------
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// Interrupt state storage
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typedef cyg_uint32 CYG_INTERRUPT_STATE;
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//--------------------------------------------------------------------------
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// Interrupt control macros
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#ifndef __thumb__
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// Note: This disables both FIQ and IRQ interrupts!
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#define HAL_DISABLE_INTERRUPTS(_old_) \
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asm volatile ( \
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"mrs %0,cpsr;" \
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"mrs r4,cpsr;" \
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"orr r4,r4,#0xC0;" \
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"msr cpsr,r4" \
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: "=r"(_old_) \
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: \
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: "r4" \
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);
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#define HAL_ENABLE_INTERRUPTS() \
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asm volatile ( \
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"mrs r3,cpsr;" \
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"bic r3,r3,#0xC0;" \
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"msr cpsr,r3" \
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: \
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: \
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: "r3" \
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);
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#define HAL_RESTORE_INTERRUPTS(_old_) \
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asm volatile ( \
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"mrs r3,cpsr;" \
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"and r4,%0,#0xC0;" \
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"bic r3,r3,#0xC0;" \
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"orr r3,r3,r4;" \
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"msr cpsr,r3" \
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: \
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: "r"(_old_) \
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: "r3", "r4" \
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);
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#define HAL_QUERY_INTERRUPTS(_old_) \
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asm volatile ( \
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"mrs r4,cpsr;" \
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"and r4,r4,#0xC0;" \
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"eor %0,r4,#0xC0;" \
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: "=r"(_old_) \
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: \
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: "r4" \
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);
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#else // __thumb__
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// Thumb mode does not have access to the PSR registers;
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#if 0 // These don't seem to always work
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#define HAL_DISABLE_INTERRUPTS(_old_) \
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asm volatile ( \
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"ldr r4,=10f;" \
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"bx r4;" \
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".code 32;" \
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"10:;" \
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"mrs %0,cpsr;" \
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"mrs r4,cpsr;" \
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"orr r4,r4,#0xC0;" \
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"msr cpsr,r4;" \
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"ldr r4,=10f+1;" \
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"bx r4;" \
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".code 16;" \
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"10:;" \
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: "=r"(_old_) \
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: \
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: "r4" \
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);
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#define HAL_ENABLE_INTERRUPTS() \
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asm volatile ( \
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"ldr r3,=10f;" \
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"bx r3;" \
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".code 32;" \
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"10:;" \
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"mrs r3,cpsr;" \
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"bic r3,r3,#0xC0;" \
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"msr cpsr,r3;" \
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"ldr r3,=10f+1;" \
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"bx r3;" \
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".code 16;" \
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"10:;" \
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: \
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: \
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: "r3" \
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);
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#define HAL_RESTORE_INTERRUPTS(_old_) \
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asm volatile ( \
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"ldr r3,=10f;" \
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"bx r3;" \
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".code 32;" \
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"10:;" \
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"mrs r3,cpsr;" \
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"and r4,%0,#0xC0;" \
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"bic r3,r3,#0xC0;" \
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"orr r3,r3,r4;" \
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"msr cpsr,r3;" \
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"ldr r3,=10f+1;" \
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"bx r3;" \
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".code 16;" \
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"10:;" \
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: \
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: "r"(_old_) \
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: "r3", "r4" \
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);
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#define HAL_QUERY_INTERRUPTS(_old_) \
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asm volatile ( \
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"ldr r4,=10f;" \
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"bx r4;" \
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".code 32;" \
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"10:;" \
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"mrs r4,cpsr;" \
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"and r4,r4,#0xC0;" \
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"eor %0,r4,#0xC0;" \
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"ldr r4,=10f+1;" \
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"bx r4;" \
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".code 16;" \
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"10:;" \
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: "=r"(_old_) \
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: \
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: "r4" \
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);
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#else
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externC cyg_uint32 hal_disable_interrupts(void);
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externC void hal_enable_interrupts(void);
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| 284 |
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externC void hal_restore_interrupts(cyg_uint32);
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| 285 |
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externC cyg_uint32 hal_query_interrupts(void);
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| 286 |
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| 287 |
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#define HAL_DISABLE_INTERRUPTS(_old_) \
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| 288 |
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_old_ = hal_disable_interrupts();
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| 290 |
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#define HAL_ENABLE_INTERRUPTS() \
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hal_enable_interrupts();
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#define HAL_RESTORE_INTERRUPTS(_old_) \
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| 294 |
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hal_restore_interrupts(_old_);
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| 296 |
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#define HAL_QUERY_INTERRUPTS(_old_) \
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| 297 |
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_old_ = hal_query_interrupts();
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| 298 |
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#endif
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| 299 |
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#endif // __thumb__
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| 302 |
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//--------------------------------------------------------------------------
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| 303 |
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// Routine to execute DSRs using separate interrupt stack
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| 304 |
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| 305 |
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#ifdef CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK
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| 306 |
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externC void hal_interrupt_stack_call_pending_DSRs(void);
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| 307 |
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#define HAL_INTERRUPT_STACK_CALL_PENDING_DSRS() \
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| 308 |
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hal_interrupt_stack_call_pending_DSRs()
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| 309 |
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| 310 |
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// these are offered solely for stack usage testing
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| 311 |
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// if they are not defined, then there is no interrupt stack.
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| 312 |
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#define HAL_INTERRUPT_STACK_BASE cyg_interrupt_stack_base
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#define HAL_INTERRUPT_STACK_TOP cyg_interrupt_stack
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// use them to declare these extern however you want:
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| 315 |
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// extern char HAL_INTERRUPT_STACK_BASE[];
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| 316 |
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// extern char HAL_INTERRUPT_STACK_TOP[];
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| 317 |
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// is recommended
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| 318 |
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#endif
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| 319 |
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| 320 |
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//--------------------------------------------------------------------------
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| 321 |
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// Vector translation.
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| 322 |
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| 323 |
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#ifndef HAL_TRANSLATE_VECTOR
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| 324 |
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#define HAL_TRANSLATE_VECTOR(_vector_,_index_) \
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| 325 |
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(_index_) = (_vector_)
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| 326 |
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#endif
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| 327 |
|
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| 328 |
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//--------------------------------------------------------------------------
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| 329 |
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// Interrupt and VSR attachment macros
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| 330 |
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| 331 |
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#define HAL_INTERRUPT_IN_USE( _vector_, _state_) \
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| 332 |
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CYG_MACRO_START \
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| 333 |
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cyg_uint32 _index_; \
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| 334 |
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HAL_TRANSLATE_VECTOR ((_vector_), _index_); \
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\
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| 336 |
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if( hal_interrupt_handlers[_index_] == (CYG_ADDRESS)hal_default_isr ) \
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| 337 |
|
|
(_state_) = 0; \
|
| 338 |
|
|
else \
|
| 339 |
|
|
(_state_) = 1; \
|
| 340 |
|
|
CYG_MACRO_END
|
| 341 |
|
|
|
| 342 |
|
|
#define HAL_INTERRUPT_ATTACH( _vector_, _isr_, _data_, _object_ ) \
|
| 343 |
|
|
CYG_MACRO_START \
|
| 344 |
|
|
if( hal_interrupt_handlers[_vector_] == (CYG_ADDRESS)hal_default_isr ) \
|
| 345 |
|
|
{ \
|
| 346 |
|
|
hal_interrupt_handlers[_vector_] = (CYG_ADDRESS)_isr_; \
|
| 347 |
|
|
hal_interrupt_data[_vector_] = (CYG_ADDRWORD) _data_; \
|
| 348 |
|
|
hal_interrupt_objects[_vector_] = (CYG_ADDRESS)_object_; \
|
| 349 |
|
|
} \
|
| 350 |
|
|
CYG_MACRO_END
|
| 351 |
|
|
|
| 352 |
|
|
#define HAL_INTERRUPT_DETACH( _vector_, _isr_ ) \
|
| 353 |
|
|
CYG_MACRO_START \
|
| 354 |
|
|
if( hal_interrupt_handlers[_vector_] == (CYG_ADDRESS)_isr_ ) \
|
| 355 |
|
|
{ \
|
| 356 |
|
|
hal_interrupt_handlers[_vector_] = (CYG_ADDRESS)hal_default_isr; \
|
| 357 |
|
|
hal_interrupt_data[_vector_] = 0; \
|
| 358 |
|
|
hal_interrupt_objects[_vector_] = 0; \
|
| 359 |
|
|
} \
|
| 360 |
|
|
CYG_MACRO_END
|
| 361 |
|
|
|
| 362 |
|
|
#define HAL_VSR_GET( _vector_, _pvsr_ ) \
|
| 363 |
|
|
*(CYG_ADDRESS *)(_pvsr_) = hal_vsr_table[_vector_];
|
| 364 |
|
|
|
| 365 |
|
|
|
| 366 |
|
|
#define HAL_VSR_SET( _vector_, _vsr_, _poldvsr_ ) \
|
| 367 |
|
|
CYG_MACRO_START \
|
| 368 |
|
|
if( _poldvsr_ != NULL ) \
|
| 369 |
|
|
*(CYG_ADDRESS *)_poldvsr_ = hal_vsr_table[_vector_]; \
|
| 370 |
|
|
hal_vsr_table[_vector_] = (CYG_ADDRESS)_vsr_; \
|
| 371 |
|
|
CYG_MACRO_END
|
| 372 |
|
|
|
| 373 |
|
|
//--------------------------------------------------------------------------
|
| 374 |
|
|
// Interrupt controller access
|
| 375 |
|
|
|
| 376 |
|
|
externC void hal_interrupt_mask(int);
|
| 377 |
|
|
externC void hal_interrupt_unmask(int);
|
| 378 |
|
|
externC void hal_interrupt_acknowledge(int);
|
| 379 |
|
|
externC void hal_interrupt_configure(int, int, int);
|
| 380 |
|
|
externC void hal_interrupt_set_level(int, int);
|
| 381 |
|
|
|
| 382 |
|
|
#define HAL_INTERRUPT_MASK( _vector_ ) \
|
| 383 |
|
|
hal_interrupt_mask( _vector_ )
|
| 384 |
|
|
#define HAL_INTERRUPT_UNMASK( _vector_ ) \
|
| 385 |
|
|
hal_interrupt_unmask( _vector_ )
|
| 386 |
|
|
#define HAL_INTERRUPT_ACKNOWLEDGE( _vector_ ) \
|
| 387 |
|
|
hal_interrupt_acknowledge( _vector_ )
|
| 388 |
|
|
#define HAL_INTERRUPT_CONFIGURE( _vector_, _level_, _up_ ) \
|
| 389 |
|
|
hal_interrupt_configure( _vector_, _level_, _up_ )
|
| 390 |
|
|
#define HAL_INTERRUPT_SET_LEVEL( _vector_, _level_ ) \
|
| 391 |
|
|
hal_interrupt_set_level( _vector_, _level_ )
|
| 392 |
|
|
|
| 393 |
|
|
//--------------------------------------------------------------------------
|
| 394 |
|
|
// Clock control
|
| 395 |
|
|
|
| 396 |
|
|
externC void hal_clock_initialize(cyg_uint32);
|
| 397 |
|
|
externC void hal_clock_read(cyg_uint32 *);
|
| 398 |
|
|
externC void hal_clock_reset(cyg_uint32, cyg_uint32);
|
| 399 |
|
|
|
| 400 |
|
|
#define HAL_CLOCK_INITIALIZE( _period_ ) hal_clock_initialize( _period_ )
|
| 401 |
|
|
#define HAL_CLOCK_RESET( _vec_, _period_ ) hal_clock_reset( _vec_, _period_ )
|
| 402 |
|
|
#define HAL_CLOCK_READ( _pvalue_ ) hal_clock_read( _pvalue_ )
|
| 403 |
|
|
#ifdef CYGVAR_KERNEL_COUNTERS_CLOCK_LATENCY
|
| 404 |
|
|
# ifndef HAL_CLOCK_LATENCY
|
| 405 |
|
|
# define HAL_CLOCK_LATENCY( _pvalue_ ) HAL_CLOCK_READ( (cyg_uint32 *)_pvalue_ )
|
| 406 |
|
|
# endif
|
| 407 |
|
|
#endif
|
| 408 |
|
|
|
| 409 |
|
|
//--------------------------------------------------------------------------
|
| 410 |
|
|
#endif // ifndef CYGONCE_HAL_INTR_H
|
| 411 |
|
|
// End of hal_intr.h
|
