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//=============================================================================
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//
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// MLT linker script for ARM
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//
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//=============================================================================
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//####ECOSGPLCOPYRIGHTBEGIN####
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// -------------------------------------------
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// This file is part of eCos, the Embedded Configurable Operating System.
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// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
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//
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// eCos is free software; you can redistribute it and/or modify it under
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// the terms of the GNU General Public License as published by the Free
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// Software Foundation; either version 2 or (at your option) any later version.
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//
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// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// for more details.
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//
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// You should have received a copy of the GNU General Public License along
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// with eCos; if not, write to the Free Software Foundation, Inc.,
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// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
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//
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// As a special exception, if other files instantiate templates or use macros
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// or inline functions from this file, or you compile this file and link it
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// with other works to produce a work based on this file, this file does not
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// by itself cause the resulting work to be covered by the GNU General Public
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// License. However the source code for this file must still be made available
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// in accordance with section (3) of the GNU General Public License.
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//
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// This exception does not invalidate any other reasons why a work based on
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// this file might be covered by the GNU General Public License.
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//
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// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
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// at http://sources.redhat.com/ecos/ecos-license/
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// -------------------------------------------
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//####ECOSGPLCOPYRIGHTEND####
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//=============================================================================
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#include
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STARTUP(vectors.o)
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ENTRY(reset_vector)
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INPUT(extras.o)
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#if (__GNUC__ >= 3)
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GROUP(libtarget.a libgcc.a libsupc++.a)
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#else
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GROUP(libtarget.a libgcc.a)
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#endif
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#if defined(__ARMEB__)
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OUTPUT_FORMAT(elf32-bigarm)
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#endif
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#if defined(CYG_HAL_STARTUP_ROM) \
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&& defined(CYGPKG_HAL_ARM_PID) \
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&& defined(__ARMEB__)
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// Note: This is only needed when the PID board is used in BE mode without
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// the proper ROM controller part.
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//
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// In big-endian mode, merge .RODATA sections into the .DATA section. This
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// causes the data in these sections to be copied to RAM. When the CPU
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// makes byte or halfword access to RAM, A0/A1 are modified correctly.
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// This does not happen on ROM access (unless the proper ROM controller
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// is used).
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//
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#define MERGE_IN_RODATA *(.rodata*)
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#define CYGPRI_PID_BE_WORKAROUND
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#else
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// Keep RODATA in separate sections.
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#define MERGE_IN_RODATA
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#undef CYGPRI_PID_BE_WORKAROUND
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#endif
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#define ALIGN_LMA 4
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#define FOLLOWING(_section_) AT ((LOADADDR (_section_) + SIZEOF (_section_) + ALIGN_LMA - 1) & ~ (ALIGN_LMA - 1))
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#define LMA_EQ_VMA
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#define FORCE_OUTPUT . = .
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// Some versions of gcc define "arm" which causes problems with .note.arm.ident
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#undef arm
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#define SECTIONS_BEGIN \
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/* Debug information */ \
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.debug_aranges 0 : { *(.debug_aranges) } \
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.debug_pubnames 0 : { *(.debug_pubnames) } \
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.debug_info 0 : { *(.debug_info) } \
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.debug_abbrev 0 : { *(.debug_abbrev) } \
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.debug_line 0 : { *(.debug_line) } \
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.debug_frame 0 : { *(.debug_frame) } \
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.debug_str 0 : { *(.debug_str) } \
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.debug_loc 0 : { *(.debug_loc) } \
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.debug_macinfo 0 : { *(.debug_macinfo) } \
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.note.arm.ident 0 : { KEEP (*(.note.arm.ident)) }
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#define SECTION_fixed_vectors(_region_, _vma_, _lma_) \
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.fixed_vectors _vma_ : _lma_ \
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{ FORCE_OUTPUT; KEEP (*(.fixed_vectors)) } \
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> _region_
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#define SECTION_rom_vectors(_region_, _vma_, _lma_) \
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.rom_vectors _vma_ : _lma_ \
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{ __rom_vectors_vma = ABSOLUTE(.); \
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FORCE_OUTPUT; KEEP (*(.vectors)) } \
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> _region_ \
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__rom_vectors_lma = LOADADDR(.rom_vectors);
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#define SECTION_text(_region_, _vma_, _lma_) \
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.text _vma_ : _lma_ \
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{ _stext = ABSOLUTE(.); \
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PROVIDE (__stext = ABSOLUTE(.)); \
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*(.text*) *(.gnu.warning) *(.gnu.linkonce.t.*) *(.init) \
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*(.glue_7) *(.glue_7t) \
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} > _region_ \
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_etext = .; PROVIDE (__etext = .);
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#define SECTION_fini(_region_, _vma_, _lma_) \
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.fini _vma_ : _lma_ \
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{ FORCE_OUTPUT; *(.fini) } \
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> _region_
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#if defined(CYGPRI_PID_BE_WORKAROUND)
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#define SECTION_rodata(_region_, _vma_, _lma_)
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#define SECTION_rodata1(_region_, _vma_, _lma_)
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#else
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#define SECTION_rodata(_region_, _vma_, _lma_) \
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.rodata _vma_ : _lma_ \
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{ FORCE_OUTPUT; *(.rodata*) *(.gnu.linkonce.r.*) } \
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> _region_
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#define SECTION_rodata1(_region_, _vma_, _lma_) \
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.rodata1 _vma_ : _lma_ \
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{ FORCE_OUTPUT; *(.rodata1) } \
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> _region_
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#endif // CYGPRI_PID_BE_WORKAROUND
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#define SECTION_fixup(_region_, _vma_, _lma_) \
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.fixup _vma_ : _lma_ \
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{ FORCE_OUTPUT; *(.fixup) } \
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> _region_
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#define SECTION_gcc_except_table(_region_, _vma_, _lma_) \
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.gcc_except_table _vma_ : _lma_ \
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{ FORCE_OUTPUT; *(.gcc_except_table) } \
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> _region_
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#define SECTION_eh_frame(_region_, _vma_, _lma_) \
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.eh_frame _vma_ : _lma_ \
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{ \
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FORCE_OUTPUT; __EH_FRAME_BEGIN__ = .; \
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KEEP(*(.eh_frame)) \
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__FRAME_END__ = .; \
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. = . + 8; \
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} > _region_ = 0
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#define SECTION_RELOCS(_region_, _vma_, _lma_) \
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.rel.text : \
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{ \
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*(.rel.text) \
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*(.rel.text.*) \
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*(.rel.gnu.linkonce.t*) \
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} > _region_ \
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.rela.text : \
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{ \
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*(.rela.text) \
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*(.rela.text.*) \
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*(.rela.gnu.linkonce.t*) \
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} > _region_ \
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.rel.data : \
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{ \
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*(.rel.data) \
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*(.rel.data.*) \
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*(.rel.gnu.linkonce.d*) \
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} > _region_ \
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.rela.data : \
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{ \
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*(.rela.data) \
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*(.rela.data.*) \
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*(.rela.gnu.linkonce.d*) \
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} > _region_ \
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.rel.rodata : \
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{ \
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*(.rel.rodata) \
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*(.rel.rodata.*) \
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*(.rel.gnu.linkonce.r*) \
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} > _region_ \
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.rela.rodata : \
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{ \
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*(.rela.rodata) \
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*(.rela.rodata.*) \
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*(.rela.gnu.linkonce.r*) \
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} > _region_ \
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.rel.got : { *(.rel.got) } > _region_ \
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.rela.got : { *(.rela.got) } > _region_ \
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.rel.ctors : { *(.rel.ctors) } > _region_ \
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.rela.ctors : { *(.rela.ctors) } > _region_ \
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.rel.dtors : { *(.rel.dtors) } > _region_ \
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.rela.dtors : { *(.rela.dtors) } > _region_ \
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.rel.init : { *(.rel.init) } > _region_ \
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.rela.init : { *(.rela.init) } > _region_ \
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.rel.fini : { *(.rel.fini) } > _region_ \
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.rela.fini : { *(.rela.fini) } > _region_ \
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.rel.bss : { *(.rel.bss) } > _region_ \
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.rela.bss : { *(.rela.bss) } > _region_ \
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.rel.plt : { *(.rel.plt) } > _region_ \
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.rela.plt : { *(.rela.plt) } > _region_ \
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.rel.dyn : { *(.rel.dyn) } > _region_
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#define SECTION_got(_region_, _vma_, _lma_) \
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.got _vma_ : _lma_ \
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{ \
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FORCE_OUTPUT; *(.got.plt) *(.got) \
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_GOT1_START_ = ABSOLUTE (.); *(.got1) _GOT1_END_ = ABSOLUTE (.); \
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_GOT2_START_ = ABSOLUTE (.); *(.got2) _GOT2_END_ = ABSOLUTE (.); \
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} > _region_
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#define SECTION_mmu_tables(_region_, _vma_, _lma_) \
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.mmu_tables _vma_ : _lma_ \
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{ FORCE_OUTPUT; *(.mmu_tables) } \
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> _region_
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#define SECTION_sram(_region_, _vma_, _lma_) \
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.sram _vma_ : _lma_ \
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{ FORCE_OUTPUT; *(.sram*) } \
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> _region_
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#define SECTION_data(_region_, _vma_, _lma_) \
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.data _vma_ : _lma_ \
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{ __ram_data_start = ABSOLUTE (.); \
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*(.data*) *(.data1) *(.gnu.linkonce.d.*) MERGE_IN_RODATA \
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. = ALIGN (4); \
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KEEP(*( SORT (.ecos.table.*))) ; \
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. = ALIGN (4); \
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__CTOR_LIST__ = ABSOLUTE (.); KEEP (*(SORT (.ctors*))) __CTOR_END__ = ABSOLUTE (.); \
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__DTOR_LIST__ = ABSOLUTE (.); KEEP (*(SORT (.dtors*))) __DTOR_END__ = ABSOLUTE (.); \
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*(.dynamic) *(.sdata*) *(.gnu.linkonce.s.*) \
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. = ALIGN (4); *(.2ram.*) } \
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> _region_ \
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__rom_data_start = LOADADDR (.data); \
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__ram_data_end = .; PROVIDE (__ram_data_end = .); _edata = .; PROVIDE (edata = .); \
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PROVIDE (__rom_data_end = LOADADDR (.data) + SIZEOF(.data));
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#define SECTION_bss(_region_, _vma_, _lma_) \
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.bss _vma_ : _lma_ \
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{ __bss_start = ABSOLUTE (.); \
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*(.scommon) *(.dynsbss) *(.sbss*) *(.gnu.linkonce.sb.*) \
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*(.dynbss) *(.bss*) *(.gnu.linkonce.b.*) *(COMMON) \
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__bss_end = ABSOLUTE (.); } \
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> _region_
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#define SECTIONS_END . = ALIGN(4); _end = .; PROVIDE (end = .);
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#include
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#include CYGHWR_MEMORY_LAYOUT_LDI
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