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[/] [openrisc/] [trunk/] [rtos/] [ecos-2.0/] [packages/] [hal/] [arm/] [arch/] [v2_0/] [src/] [context.S] - Blame information for rev 174

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// #===========================================================================
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// #
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// #    context.S
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// #
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// #    ARM context switch code
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// #
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// #===========================================================================
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//####ECOSGPLCOPYRIGHTBEGIN####
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// -------------------------------------------
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// This file is part of eCos, the Embedded Configurable Operating System.
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// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
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//
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// eCos is free software; you can redistribute it and/or modify it under
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// the terms of the GNU General Public License as published by the Free
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// Software Foundation; either version 2 or (at your option) any later version.
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//
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// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or
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// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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// for more details.
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//
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// You should have received a copy of the GNU General Public License along
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// with eCos; if not, write to the Free Software Foundation, Inc.,
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// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
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//
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// As a special exception, if other files instantiate templates or use macros
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// or inline functions from this file, or you compile this file and link it
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// with other works to produce a work based on this file, this file does not
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// by itself cause the resulting work to be covered by the GNU General Public
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// License. However the source code for this file must still be made available
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// in accordance with section (3) of the GNU General Public License.
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//
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// This exception does not invalidate any other reasons why a work based on
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// this file might be covered by the GNU General Public License.
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//
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// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
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// at http://sources.redhat.com/ecos/ecos-license/
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// -------------------------------------------
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//####ECOSGPLCOPYRIGHTEND####
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// #===========================================================================
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// ######DESCRIPTIONBEGIN####
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// #
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// # Author(s):    nickg, gthomas
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// # Contributors: nickg, gthomas
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// # Date:         1998-09-15
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// # Purpose:      ARM context switch code
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// # Description:  This file contains implementations of the thread context
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// #               switch routines. It also contains the longjmp() and setjmp()
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// #               routines.
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// #
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// #####DESCRIPTIONEND####
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// #
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// #===========================================================================
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#include 
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#include "arm.inc"
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        .text
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// ----------------------------------------------------------------------------
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//  function declaration macro (start body in ARM mode)
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#ifdef __thumb__
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#define FUNC_START_ARM(_name_, _r_)              \
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        .code   16                              ;\
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        .thumb_func                             ;\
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        .globl _name_                           ;\
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_name_:                                         ;\
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        ldr     _r_,=_name_ ## _ARM             ;\
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        bx      _r_                             ;\
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        .code   32                              ;\
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_name_ ## _ARM:
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#else
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#define FUNC_START_ARM(_name_, _r_) \
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        .globl _name_; \
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_name_:
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#endif
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// ----------------------------------------------------------------------------
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//  hal_thread_switch_context
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//  Switch thread contexts
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//  R0 = address of sp of next thread to execute
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//  R1 = address of sp save location of current thread
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// Need to save/restore R4..R12, R13 (sp), R14 (lr)
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// Note: this is a little wasteful since r0..r3 don't need to be saved.
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// They are saved here though so that the information can match the HAL_SavedRegisters
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FUNC_START_ARM(hal_thread_switch_context, r2)
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        sub     ip,sp,#20               // skip svc_sp, svc_lr, vector, cpsr, and pc
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        stmfd   ip!,{sp,lr}
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        mov     sp,ip
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        stmfd   sp!,{r0-r10,fp,ip}
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        mrs     r2,cpsr
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        str     r2,[sp,#armreg_cpsr]
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        str     sp,[r1]                 // return new stack pointer
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#ifdef __thumb__
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        b       hal_thread_load_context_ARM // skip mode switch stuff
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#endif
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        # Now load the destination thread by dropping through
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        # to hal_thread_load_context
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// ----------------------------------------------------------------------------
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//  hal_thread_load_context
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//  Load thread context
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//  R0 = address of sp of next thread to execute
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//  Note that this function is also the second half of
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//  hal_thread_switch_context and is simply dropped into from it.
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FUNC_START_ARM(hal_thread_load_context, r2)
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        ldr     fp,[r0]                 // get context to restore
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        mrs     r0,cpsr                 // disable IRQ's
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        orr     r0,r0,#CPSR_IRQ_DISABLE|CPSR_FIQ_DISABLE
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        msr     cpsr,r0
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        ldr     r0,[fp,#armreg_cpsr]
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        msr     spsr,r0
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        ldmfd   fp,{r0-r10,fp,ip,sp,lr}
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#ifdef __thumb__
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        mrs     r1,spsr                 // r1 is scratch
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                                        // [r0 holds initial thread arg]
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        msr     cpsr,r1                 // hopefully no mode switch here!
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        bx      lr
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#else
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        movs    pc,lr                   // also restores saved PSR
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#endif
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// ----------------------------------------------------------------------------
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//  HAL longjmp, setjmp implementations
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//  hal_setjmp saves only to callee save registers 4-14
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//  and lr into buffer supplied in r0[arg0]
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FUNC_START_ARM(hal_setjmp, r2)
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        stmea   r0,{r4-r14}
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        mov     r0,#0
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#ifdef __thumb__
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        bx      lr
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#else
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        mov     pc,lr;          # return
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#endif
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//  hal_longjmp loads state from r0[arg0] and returns
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FUNC_START_ARM(hal_longjmp, r2)
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        ldmfd   r0,{r4-r14}
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        mov     r0,r1;          # return [arg1]
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#ifdef __thumb__
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        bx      lr
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#else
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        mov     pc,lr
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#endif
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// ----------------------------------------------------------------------------
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//  end of context.S

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