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#ifndef CYGONCE_HAL_CACHE_H
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#define CYGONCE_HAL_CACHE_H
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//=============================================================================
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//
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// hal_cache.h
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//
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// HAL cache control API
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//
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//=============================================================================
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//####ECOSGPLCOPYRIGHTBEGIN####
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// -------------------------------------------
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// This file is part of eCos, the Embedded Configurable Operating System.
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// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
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//
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// eCos is free software; you can redistribute it and/or modify it under
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// the terms of the GNU General Public License as published by the Free
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// Software Foundation; either version 2 or (at your option) any later version.
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//
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// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// for more details.
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//
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// You should have received a copy of the GNU General Public License along
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// with eCos; if not, write to the Free Software Foundation, Inc.,
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// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
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//
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// As a special exception, if other files instantiate templates or use macros
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// or inline functions from this file, or you compile this file and link it
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// with other works to produce a work based on this file, this file does not
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// by itself cause the resulting work to be covered by the GNU General Public
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// License. However the source code for this file must still be made available
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// in accordance with section (3) of the GNU General Public License.
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//
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// This exception does not invalidate any other reasons why a work based on
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// this file might be covered by the GNU General Public License.
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//
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// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
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// at http://sources.redhat.com/ecos/ecos-license/
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// -------------------------------------------
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//####ECOSGPLCOPYRIGHTEND####
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//=============================================================================
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//#####DESCRIPTIONBEGIN####
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//
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// Author(s): gthomas
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// Contributors:hmt, jskov
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// Travis C. Furrer <furrer@mit.edu>
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// Date: 2000-05-08
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// Purpose: Cache control API
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// Description: The macros defined here provide the HAL APIs for handling
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// cache control operations.
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// Usage:
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// #include <cyg/hal/hal_cache.h>
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// ...
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//
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//
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//####DESCRIPTIONEND####
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//
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//=============================================================================
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#include <cyg/infra/cyg_type.h>
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#include <cyg/hal/hal_mmu.h>
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//-----------------------------------------------------------------------------
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// Cache dimensions
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#if defined(CYGPKG_HAL_ARM_ARM9_ARM920T)
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# define HAL_ICACHE_SIZE 0x4000
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# define HAL_ICACHE_LINE_SIZE 32
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# define HAL_ICACHE_WAYS 64
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# define HAL_ICACHE_SETS (HAL_ICACHE_SIZE/(HAL_ICACHE_LINE_SIZE*HAL_ICACHE_WAYS))
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# define HAL_DCACHE_SIZE 0x4000
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# define HAL_DCACHE_LINE_SIZE 32
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# define HAL_DCACHE_WAYS 64
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# define HAL_DCACHE_SETS (HAL_DCACHE_SIZE/(HAL_DCACHE_LINE_SIZE*HAL_DCACHE_WAYS))
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# define HAL_WRITE_BUFFER 64
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# define CYGHWR_HAL_ARM_ARM9_CLEAN_DCACHE_INDEX
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# define CYGHWR_HAL_ARM_ARM9_CLEAN_DCACHE_INDEX_STEP 0x20
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# define CYGHWR_HAL_ARM_ARM9_CLEAN_DCACHE_INDEX_LIMIT 0x100
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#elif defined(CYGPKG_HAL_ARM_ARM9_ARM922T)
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# define HAL_ICACHE_SIZE 0x2000
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# define HAL_ICACHE_LINE_SIZE 32
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# define HAL_ICACHE_WAYS 64
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# define HAL_ICACHE_SETS (HAL_ICACHE_SIZE/(HAL_ICACHE_LINE_SIZE*HAL_ICACHE_WAYS))
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# define HAL_DCACHE_SIZE 0x2000
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# define HAL_DCACHE_LINE_SIZE 32
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# define HAL_DCACHE_WAYS 64
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# define HAL_DCACHE_SETS (HAL_DCACHE_SIZE/(HAL_DCACHE_LINE_SIZE*HAL_DCACHE_WAYS))
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# define HAL_WRITE_BUFFER 64
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# define CYGHWR_HAL_ARM_ARM9_CLEAN_DCACHE_INDEX
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# define CYGHWR_HAL_ARM_ARM9_CLEAN_DCACHE_INDEX_STEP 0x20
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# define CYGHWR_HAL_ARM_ARM9_CLEAN_DCACHE_INDEX_LIMIT 0x80
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#elif defined(CYGPKG_HAL_ARM_ARM9_ARM925T)
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# define HAL_ICACHE_SIZE 0x4000
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# define HAL_ICACHE_LINE_SIZE 16
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# define HAL_ICACHE_WAYS 2
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# define HAL_ICACHE_SETS (HAL_ICACHE_SIZE/(HAL_ICACHE_LINE_SIZE*HAL_ICACHE_WAYS))
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# define HAL_DCACHE_SIZE 0x2000
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# define HAL_DCACHE_LINE_SIZE 16
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# define HAL_DCACHE_WAYS 2
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# define HAL_DCACHE_SETS (HAL_DCACHE_SIZE/(HAL_DCACHE_LINE_SIZE*HAL_DCACHE_WAYS))
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# define HAL_WRITE_BUFFER 64
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# define CYGHWR_HAL_ARM_ARM9_CLEAN_DCACHE // has instruction to clean D-cache
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#elif defined(CYGPKG_HAL_ARM_ARM9_ARM940T)
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# define HAL_ICACHE_SIZE 0x1000
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# define HAL_ICACHE_LINE_SIZE 16
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# define HAL_ICACHE_WAYS 4
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# define HAL_ICACHE_SETS (HAL_ICACHE_SIZE/(HAL_ICACHE_LINE_SIZE*HAL_ICACHE_WAYS))
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# define HAL_DCACHE_SIZE 0x1000
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# define HAL_DCACHE_LINE_SIZE 16
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# define HAL_DCACHE_WAYS 4
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# define HAL_DCACHE_SETS (HAL_DCACHE_SIZE/(HAL_DCACHE_LINE_SIZE*HAL_DCACHE_WAYS))
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# define HAL_WRITE_BUFFER 32
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# define CYGHWR_HAL_ARM_ARM9_CLEAN_DCACHE_INDEX
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# define CYGHWR_HAL_ARM_ARM9_CLEAN_DCACHE_INDEX_STEP 0x10
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# define CYGHWR_HAL_ARM_ARM9_CLEAN_DCACHE_INDEX_LIMIT 0x40
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#elif defined(CYGPKG_HAL_ARM_ARM9_ARM966E)
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# define HAL_ICACHE_SIZE 0
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# define HAL_ICACHE_LINE_SIZE 0
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# define HAL_ICACHE_WAYS 0
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# define HAL_ICACHE_SETS (HAL_ICACHE_SIZE/(HAL_ICACHE_LINE_SIZE*HAL_ICACHE_WAYS))
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# define HAL_DCACHE_SIZE 0
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# define HAL_DCACHE_LINE_SIZE 0
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# define HAL_DCACHE_WAYS 0
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# define HAL_DCACHE_SETS (HAL_DCACHE_SIZE/(HAL_DCACHE_LINE_SIZE*HAL_DCACHE_WAYS))
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# define HAL_WRITE_BUFFER 32
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# define CYGHWR_HAL_ARM_ARM9_CLEAN_DCACHE_INDEX
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# define CYGHWR_HAL_ARM_ARM9_CLEAN_DCACHE_INDEX_STEP 0
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# define CYGHWR_HAL_ARM_ARM9_CLEAN_DCACHE_INDEX_LIMIT 0
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#else
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# error "No cache details defined"
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#endif
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// FIXME: much of the code below should make better use of
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// the definitions from hal_mmu.h
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//-----------------------------------------------------------------------------
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// Global control of Instruction cache
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#if HAL_ICACHE_SIZE != 0
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// FIXME: disable/enable instruction streaming?
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// Enable the instruction cache
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#define HAL_ICACHE_ENABLE() \
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CYG_MACRO_START \
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asm volatile ( \
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"mrc p15,0,r1,c1,c0,0;" \
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"orr r1,r1,#0x1000;" \
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"orr r1,r1,#0x0003;" /* enable ICache (also ensures */ \
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/* that MMU and alignment faults */ \
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/* are enabled) */ \
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"mcr p15,0,r1,c1,c0,0" \
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: \
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: \
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: "r1" /* Clobber list */ \
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); \
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CYG_MACRO_END
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// Disable the instruction cache (and invalidate it, required semanitcs)
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#define HAL_ICACHE_DISABLE() \
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CYG_MACRO_START \
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asm volatile ( \
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"mrc p15,0,r1,c1,c0,0;" \
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"bic r1,r1,#0x1000;" /* disable ICache (but not MMU, etc) */ \
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"mcr p15,0,r1,c1,c0,0;" \
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"mov r1,#0;" \
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"mcr p15,0,r1,c7,c5,0;" /* flush ICache */ \
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"nop;" /* next few instructions may be via cache */ \
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"nop;" \
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"nop;" \
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"nop;" \
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"nop;" \
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"nop" \
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: \
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: \
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: "r1" /* Clobber list */ \
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); \
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CYG_MACRO_END
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// Query the state of the instruction cache
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#define HAL_ICACHE_IS_ENABLED(_state_) \
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CYG_MACRO_START \
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register cyg_uint32 reg; \
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asm volatile ("mrc p15,0,%0,c1,c0,0" \
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: "=r"(reg) \
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: \
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); \
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(_state_) = (0 != (0x1000 & reg)); /* Bit 12 is ICache enable */ \
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CYG_MACRO_END
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// Invalidate the entire cache
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#define HAL_ICACHE_INVALIDATE_ALL() \
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CYG_MACRO_START \
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/* this macro can discard dirty cache lines (N/A for ICache) */ \
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asm volatile ( \
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"mov r1,#0;" \
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"mcr p15,0,r1,c7,c5,0;" /* flush ICache */ \
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"mcr p15,0,r1,c8,c5,0;" /* flush ITLB only */ \
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"nop;" /* next few instructions may be via cache */ \
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"nop;" \
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"nop;" \
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"nop;" \
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"nop;" \
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"nop;" \
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: \
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: \
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: "r1" /* Clobber list */ \
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); \
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CYG_MACRO_END
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// Synchronize the contents of the cache with memory.
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// (which includes flushing out pending writes)
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#define HAL_ICACHE_SYNC() \
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CYG_MACRO_START \
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HAL_DCACHE_SYNC(); /* ensure data gets to RAM */ \
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HAL_ICACHE_INVALIDATE_ALL(); /* forget all we know */ \
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CYG_MACRO_END
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#else
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#define HAL_ICACHE_ENABLE()
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#define HAL_ICACHE_DISABLE()
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#define HAL_ICACHE_IS_ENABLED(_state_) ((_state_) = 0)
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#define HAL_ICACHE_INVALIDATE_ALL()
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#define HAL_ICACHE_SYNC()
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#endif
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// Set the instruction cache refill burst size
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//#define HAL_ICACHE_BURST_SIZE(_size_)
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// Load the contents of the given address range into the instruction cache
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// and then lock the cache so that it stays there.
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//#define HAL_ICACHE_LOCK(_base_, _size_)
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// Undo a previous lock operation
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//#define HAL_ICACHE_UNLOCK(_base_, _size_)
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// Unlock entire cache
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//#define HAL_ICACHE_UNLOCK_ALL()
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//-----------------------------------------------------------------------------
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// Instruction cache line control
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// Invalidate cache lines in the given range without writing to memory.
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//#define HAL_ICACHE_INVALIDATE( _base_ , _size_ )
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//-----------------------------------------------------------------------------
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// Global control of data cache
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#if HAL_DCACHE_SIZE != 0
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// Enable the data cache
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#define HAL_DCACHE_ENABLE() \
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CYG_MACRO_START \
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asm volatile ( \
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"mrc p15,0,r1,c1,c0,0;" \
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"orr r1,r1,#0x000F;" /* enable DCache (also ensures */ \
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/* the MMU, alignment faults, and */ \
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/* write buffer are enabled) */ \
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"mcr p15,0,r1,c1,c0,0" \
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: \
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: \
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: "r1" /* Clobber list */ \
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); \
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CYG_MACRO_END
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// Disable the data cache (and invalidate it, required semanitcs)
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#define HAL_DCACHE_DISABLE() \
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CYG_MACRO_START \
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asm volatile ( \
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"mrc p15,0,r1,c1,c0,0;" \
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"bic r1,r1,#0x000C;" /* disable DCache AND write buffer */ \
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/* but not MMU and alignment faults */ \
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"mcr p15,0,r1,c1,c0,0;" \
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"mov r1,#0;" \
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"mcr p15,0,r1,c7,c6,0" /* clear data cache */ \
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: \
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: \
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: "r1" /* Clobber list */ \
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); \
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CYG_MACRO_END
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// Query the state of the data cache
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#define HAL_DCACHE_IS_ENABLED(_state_) \
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CYG_MACRO_START \
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register int reg; \
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asm volatile ("mrc p15,0,%0,c1,c0,0;" \
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: "=r"(reg) \
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: \
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); \
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(_state_) = (0 != (4 & reg)); /* Bit 2 is DCache enable */ \
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CYG_MACRO_END
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// Flush the entire dcache (and then both TLBs, just in case)
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#define HAL_DCACHE_INVALIDATE_ALL() \
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|
CYG_MACRO_START /* this macro can discard dirty cache lines. */ \
|
| 321 |
|
|
asm volatile ( \
|
| 322 |
|
|
"mov r0,#0;" \
|
| 323 |
|
|
"mcr p15,0,r0,c7,c6,0;" /* flush d-cache */ \
|
| 324 |
|
|
"mcr p15,0,r0,c8,c7,0;" /* flush i+d-TLBs */ \
|
| 325 |
|
|
: \
|
| 326 |
|
|
: \
|
| 327 |
|
|
: "r0","memory" /* clobber list */); \
|
| 328 |
|
|
CYG_MACRO_END
|
| 329 |
|
|
|
| 330 |
|
|
// Synchronize the contents of the cache with memory.
|
| 331 |
|
|
#ifdef CYGHWR_HAL_ARM_ARM9_CLEAN_DCACHE
|
| 332 |
|
|
#define HAL_DCACHE_SYNC() \
|
| 333 |
|
|
CYG_MACRO_START \
|
| 334 |
|
|
asm volatile ( \
|
| 335 |
|
|
"mov r0, #0;" \
|
| 336 |
|
|
"mcr p15,0,r0,c7,c10,0;" /* clean DCache */ \
|
| 337 |
|
|
"1: mrc p15,0,r0,c15,c4,0;" /* wait for dirty flag to clear */ \
|
| 338 |
|
|
"ands r0,r0,#0x80000000;" \
|
| 339 |
|
|
"bne 1b;" \
|
| 340 |
|
|
"mov r0,#0;" \
|
| 341 |
|
|
"mcr p15,0,r0,c7,c6,0;" /* flush DCache */ \
|
| 342 |
|
|
"mcr p15,0,r0,c7,c10,4;" /* and drain the write buffer */ \
|
| 343 |
|
|
: \
|
| 344 |
|
|
: \
|
| 345 |
|
|
: "r0" /* Clobber list */ \
|
| 346 |
|
|
); \
|
| 347 |
|
|
CYG_MACRO_END
|
| 348 |
|
|
#elif defined(CYGHWR_HAL_ARM_ARM9_CLEAN_DCACHE_INDEX)
|
| 349 |
|
|
#define HAL_DCACHE_SYNC() \
|
| 350 |
|
|
CYG_MACRO_START \
|
| 351 |
|
|
cyg_uint32 _tmp1, _tmp2; \
|
| 352 |
|
|
asm volatile ( \
|
| 353 |
|
|
"mov %0, #0;" \
|
| 354 |
|
|
"1: " \
|
| 355 |
|
|
"mov %1, #0;" \
|
| 356 |
|
|
"2: " \
|
| 357 |
|
|
"orr r0,%0,%1;" \
|
| 358 |
|
|
"mcr p15,0,r0,c7,c14,2;" /* clean index in DCache */ \
|
| 359 |
|
|
"add %1,%1,%2;" \
|
| 360 |
|
|
"cmp %1,%3;" \
|
| 361 |
|
|
"bne 2b;" \
|
| 362 |
|
|
"add %0,%0,#0x04000000;" /* get to next index */ \
|
| 363 |
|
|
"cmp %0,#0;" \
|
| 364 |
|
|
"bne 1b;" \
|
| 365 |
|
|
"mcr p15,0,r0,c7,c10,4;" /* drain the write buffer */ \
|
| 366 |
|
|
: "=r" (_tmp1), "=r" (_tmp2) \
|
| 367 |
|
|
: "I" (CYGHWR_HAL_ARM_ARM9_CLEAN_DCACHE_INDEX_STEP), \
|
| 368 |
|
|
"I" (CYGHWR_HAL_ARM_ARM9_CLEAN_DCACHE_INDEX_LIMIT) \
|
| 369 |
|
|
: "r0" /* Clobber list */ \
|
| 370 |
|
|
); \
|
| 371 |
|
|
CYG_MACRO_END
|
| 372 |
|
|
#else
|
| 373 |
|
|
# error "Don't know how to sync Dcache"
|
| 374 |
|
|
#endif
|
| 375 |
|
|
|
| 376 |
|
|
#else
|
| 377 |
|
|
|
| 378 |
|
|
#define HAL_DCACHE_ENABLE()
|
| 379 |
|
|
#define HAL_DCACHE_DISABLE()
|
| 380 |
|
|
#define HAL_DCACHE_IS_ENABLED(_state_) ((_state_) = 0)
|
| 381 |
|
|
#define HAL_DCACHE_INVALIDATE_ALL()
|
| 382 |
|
|
#define HAL_DCACHE_SYNC()
|
| 383 |
|
|
|
| 384 |
|
|
#endif
|
| 385 |
|
|
|
| 386 |
|
|
|
| 387 |
|
|
// Set the data cache refill burst size
|
| 388 |
|
|
//#define HAL_DCACHE_BURST_SIZE(_size_)
|
| 389 |
|
|
|
| 390 |
|
|
// Set the data cache write mode
|
| 391 |
|
|
//#define HAL_DCACHE_WRITE_MODE( _mode_ )
|
| 392 |
|
|
|
| 393 |
|
|
#define HAL_DCACHE_WRITETHRU_MODE 0
|
| 394 |
|
|
#define HAL_DCACHE_WRITEBACK_MODE 1
|
| 395 |
|
|
|
| 396 |
|
|
// Get the current writeback mode - or only writeback mode if fixed
|
| 397 |
|
|
#define HAL_DCACHE_QUERY_WRITE_MODE( _mode_ ) CYG_MACRO_START \
|
| 398 |
|
|
_mode_ = HAL_DCACHE_WRITEBACK_MODE; \
|
| 399 |
|
|
CYG_MACRO_END
|
| 400 |
|
|
|
| 401 |
|
|
// Load the contents of the given address range into the data cache
|
| 402 |
|
|
// and then lock the cache so that it stays there.
|
| 403 |
|
|
//#define HAL_DCACHE_LOCK(_base_, _size_)
|
| 404 |
|
|
|
| 405 |
|
|
// Undo a previous lock operation
|
| 406 |
|
|
//#define HAL_DCACHE_UNLOCK(_base_, _size_)
|
| 407 |
|
|
|
| 408 |
|
|
// Unlock entire cache
|
| 409 |
|
|
//#define HAL_DCACHE_UNLOCK_ALL()
|
| 410 |
|
|
|
| 411 |
|
|
//-----------------------------------------------------------------------------
|
| 412 |
|
|
// Data cache line control
|
| 413 |
|
|
|
| 414 |
|
|
// Allocate cache lines for the given address range without reading its
|
| 415 |
|
|
// contents from memory.
|
| 416 |
|
|
//#define HAL_DCACHE_ALLOCATE( _base_ , _size_ )
|
| 417 |
|
|
|
| 418 |
|
|
// Write dirty cache lines to memory and invalidate the cache entries
|
| 419 |
|
|
// for the given address range.
|
| 420 |
|
|
// ---- this seems not to work despite the documentation ---
|
| 421 |
|
|
//#define HAL_DCACHE_FLUSH( _base_ , _size_ )
|
| 422 |
|
|
//CYG_MACRO_START
|
| 423 |
|
|
// HAL_DCACHE_STORE( _base_ , _size_ );
|
| 424 |
|
|
// HAL_DCACHE_INVALIDATE( _base_ , _size_ );
|
| 425 |
|
|
//CYG_MACRO_END
|
| 426 |
|
|
|
| 427 |
|
|
// Invalidate cache lines in the given range without writing to memory.
|
| 428 |
|
|
// ---- this seems not to work despite the documentation ---
|
| 429 |
|
|
//#define HAL_DCACHE_INVALIDATE( _base_ , _size_ )
|
| 430 |
|
|
//CYG_MACRO_START
|
| 431 |
|
|
// register int addr, enda;
|
| 432 |
|
|
// for ( addr = (~(HAL_DCACHE_LINE_SIZE - 1)) & (int)(_base_),
|
| 433 |
|
|
// enda = (int)(_base_) + (_size_);
|
| 434 |
|
|
// addr < enda ;
|
| 435 |
|
|
// addr += HAL_DCACHE_LINE_SIZE )
|
| 436 |
|
|
// {
|
| 437 |
|
|
// asm volatile (
|
| 438 |
|
|
// "mcr p15,0,%0,c7,c6,1;" /* flush entry away */
|
| 439 |
|
|
// :
|
| 440 |
|
|
// : "r"(addr)
|
| 441 |
|
|
// : "memory"
|
| 442 |
|
|
// );
|
| 443 |
|
|
// }
|
| 444 |
|
|
//CYG_MACRO_END
|
| 445 |
|
|
|
| 446 |
|
|
// Write dirty cache lines to memory for the given address range.
|
| 447 |
|
|
// ---- this seems not to work despite the documentation ---
|
| 448 |
|
|
//#define HAL_DCACHE_STORE( _base_ , _size_ )
|
| 449 |
|
|
//CYG_MACRO_START
|
| 450 |
|
|
// register int addr, enda;
|
| 451 |
|
|
// for ( addr = (~(HAL_DCACHE_LINE_SIZE - 1)) & (int)(_base_),
|
| 452 |
|
|
// enda = (int)(_base_) + (_size_);
|
| 453 |
|
|
// addr < enda ;
|
| 454 |
|
|
// addr += HAL_DCACHE_LINE_SIZE )
|
| 455 |
|
|
// {
|
| 456 |
|
|
// asm volatile ("mcr p15,0,%0,c7,c10,1;" /* push entry to RAM */
|
| 457 |
|
|
// :
|
| 458 |
|
|
// : "r"(addr)
|
| 459 |
|
|
// : "memory"
|
| 460 |
|
|
// );
|
| 461 |
|
|
// }
|
| 462 |
|
|
//CYG_MACRO_END
|
| 463 |
|
|
|
| 464 |
|
|
// Preread the given range into the cache with the intention of reading
|
| 465 |
|
|
// from it later.
|
| 466 |
|
|
//#define HAL_DCACHE_READ_HINT( _base_ , _size_ )
|
| 467 |
|
|
|
| 468 |
|
|
// Preread the given range into the cache with the intention of writing
|
| 469 |
|
|
// to it later.
|
| 470 |
|
|
//#define HAL_DCACHE_WRITE_HINT( _base_ , _size_ )
|
| 471 |
|
|
|
| 472 |
|
|
// Allocate and zero the cache lines associated with the given range.
|
| 473 |
|
|
//#define HAL_DCACHE_ZERO( _base_ , _size_ )
|
| 474 |
|
|
|
| 475 |
|
|
//-----------------------------------------------------------------------------
|
| 476 |
|
|
// Cache controls for safely disabling/reenabling caches around execution
|
| 477 |
|
|
// of relocated code.
|
| 478 |
|
|
|
| 479 |
|
|
#define HAL_FLASH_CACHES_OFF(_d_, _i_) \
|
| 480 |
|
|
CYG_MACRO_START \
|
| 481 |
|
|
HAL_ICACHE_IS_ENABLED(_i_); \
|
| 482 |
|
|
HAL_DCACHE_IS_ENABLED(_d_); \
|
| 483 |
|
|
HAL_ICACHE_INVALIDATE_ALL(); \
|
| 484 |
|
|
HAL_ICACHE_DISABLE(); \
|
| 485 |
|
|
HAL_DCACHE_SYNC(); \
|
| 486 |
|
|
HAL_DCACHE_INVALIDATE_ALL(); \
|
| 487 |
|
|
HAL_DCACHE_DISABLE(); \
|
| 488 |
|
|
CYG_MACRO_END
|
| 489 |
|
|
|
| 490 |
|
|
#define HAL_FLASH_CACHES_ON(_d_, _i_) \
|
| 491 |
|
|
CYG_MACRO_START \
|
| 492 |
|
|
if (_d_) HAL_DCACHE_ENABLE(); \
|
| 493 |
|
|
if (_i_) HAL_ICACHE_ENABLE(); \
|
| 494 |
|
|
CYG_MACRO_END
|
| 495 |
|
|
|
| 496 |
|
|
//-----------------------------------------------------------------------------
|
| 497 |
|
|
// Virtual<->Physical translations
|
| 498 |
|
|
#ifndef HAL_VIRT_TO_PHYS_ADDRESS
|
| 499 |
|
|
extern cyg_uint32 hal_virt_to_phys_address(cyg_uint32 phys);
|
| 500 |
|
|
#define HAL_VIRT_TO_PHYS_ADDRESS(_va, _pa) \
|
| 501 |
|
|
_pa = hal_virt_to_phys_address(_va)
|
| 502 |
|
|
#endif
|
| 503 |
|
|
//-----------------------------------------------------------------------------
|
| 504 |
|
|
#endif // ifndef CYGONCE_HAL_CACHE_H
|
| 505 |
|
|
// End of hal_cache.h
|
