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//==========================================================================
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//
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// at91_misc.c
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//
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// HAL misc board support code for Atmel AT91/EB40
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//
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//==========================================================================
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//####ECOSGPLCOPYRIGHTBEGIN####
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// -------------------------------------------
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// This file is part of eCos, the Embedded Configurable Operating System.
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// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
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//
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// eCos is free software; you can redistribute it and/or modify it under
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// the terms of the GNU General Public License as published by the Free
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// Software Foundation; either version 2 or (at your option) any later version.
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//
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// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// for more details.
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//
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// You should have received a copy of the GNU General Public License along
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// with eCos; if not, write to the Free Software Foundation, Inc.,
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// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
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//
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// As a special exception, if other files instantiate templates or use macros
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// or inline functions from this file, or you compile this file and link it
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// with other works to produce a work based on this file, this file does not
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// by itself cause the resulting work to be covered by the GNU General Public
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// License. However the source code for this file must still be made available
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// in accordance with section (3) of the GNU General Public License.
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//
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// This exception does not invalidate any other reasons why a work based on
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// this file might be covered by the GNU General Public License.
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//
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// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
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// at http://sources.redhat.com/ecos/ecos-license/
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// -------------------------------------------
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//####ECOSGPLCOPYRIGHTEND####
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//==========================================================================
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//#####DESCRIPTIONBEGIN####
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//
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// Author(s): gthomas
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// Contributors: gthomas, jskov
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// Date: 2001-07-12
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// Purpose: HAL board support
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// Description: Implementations of HAL board interfaces
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//
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//####DESCRIPTIONEND####
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//
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//========================================================================*/
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#include <pkgconf/hal.h>
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#include <cyg/infra/cyg_type.h> // base types
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#include <cyg/infra/cyg_trac.h> // tracing macros
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#include <cyg/infra/cyg_ass.h> // assertion macros
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#include <cyg/hal/hal_io.h> // IO macros
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#include <cyg/hal/hal_arch.h> // Register state info
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#include <cyg/hal/hal_diag.h>
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#include <cyg/hal/hal_intr.h> // necessary?
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#include <cyg/hal/hal_cache.h>
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#include <cyg/hal/hal_if.h> // calling interface
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#include <cyg/hal/hal_misc.h> // helper functions
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#ifdef CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT
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#include <cyg/hal/drv_api.h> // HAL ISR support
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#endif
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#include <cyg/hal/plf_io.h> // platform registers
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static cyg_uint32 _period;
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void hal_clock_initialize(cyg_uint32 period)
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{
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CYG_ADDRESS timer = AT91_TC+AT91_TC_TC0;
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CYG_ASSERT(period < 0x10000, "Invalid clock period");
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// Disable counter
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HAL_WRITE_UINT32(timer+AT91_TC_CCR, AT91_TC_CCR_CLKDIS);
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// Set registers
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HAL_WRITE_UINT32(timer+AT91_TC_CMR, AT91_TC_CMR_CPCTRG | // Reset counter on CPC
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AT91_TC_CMR_CLKS_MCK32); // 1 MHz
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HAL_WRITE_UINT32(timer+AT91_TC_RC, period);
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// Start timer
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HAL_WRITE_UINT32(timer+AT91_TC_CCR, AT91_TC_CCR_TRIG | AT91_TC_CCR_CLKEN);
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// Enable timer 0 interrupt
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HAL_WRITE_UINT32(timer+AT91_TC_IER, AT91_TC_IER_CPC);
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}
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void hal_clock_reset(cyg_uint32 vector, cyg_uint32 period)
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{
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CYG_ADDRESS timer = AT91_TC+AT91_TC_TC0;
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cyg_uint32 sr;
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CYG_ASSERT(period < 0x10000, "Invalid clock period");
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HAL_READ_UINT32(timer+AT91_TC_SR, sr); // Clear interrupt
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HAL_INTERRUPT_ACKNOWLEDGE(CYGNUM_HAL_INTERRUPT_RTC);
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if (period != _period) {
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hal_clock_initialize(period);
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}
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_period = period;
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}
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void hal_clock_read(cyg_uint32 *pvalue)
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{
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CYG_ADDRESS timer = AT91_TC+AT91_TC_TC0;
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cyg_uint32 val;
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HAL_READ_UINT32(timer+AT91_TC_CV, val);
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*pvalue = val;
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}
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// -------------------------------------------------------------------------
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//
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// Delay for some number of micro-seconds
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// Use timer #2 in 1MHz mode
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//
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void hal_delay_us(cyg_int32 usecs)
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{
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CYG_ADDRESS timer = AT91_TC+AT91_TC_TC2;
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cyg_uint32 stat;
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// Disable counter
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HAL_WRITE_UINT32(timer+AT91_TC_CCR, AT91_TC_CCR_CLKDIS);
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// Set registers
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HAL_WRITE_UINT32(timer+AT91_TC_CMR, AT91_TC_CMR_CLKS_MCK32); // 1MHz
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HAL_WRITE_UINT32(timer+AT91_TC_RA, 0);
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HAL_WRITE_UINT32(timer+AT91_TC_RC, usecs);
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// Start timer
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HAL_WRITE_UINT32(timer+AT91_TC_CCR, AT91_TC_CCR_TRIG | AT91_TC_CCR_CLKEN);
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// Wait for the compare
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do {
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HAL_READ_UINT32(timer+AT91_TC_SR, stat);
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} while ((stat & AT91_TC_SR_CPC) == 0);
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}
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// -------------------------------------------------------------------------
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// Hardware init
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void hal_hardware_init(void)
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{
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// Set up eCos/ROM interfaces
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hal_if_init();
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// Reset all interrupts
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HAL_WRITE_UINT32(AT91_AIC+AT91_AIC_IDCR, 0xFFFFFFFF);
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// Make sure interrupt controller is happy
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HAL_WRITE_UINT32(AT91_AIC+AT91_AIC_EOI, 0xFFFFFFFF);
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}
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//
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// This routine is called to respond to a hardware interrupt (IRQ). It
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// should interrogate the hardware and return the IRQ vector number.
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int hal_IRQ_handler(void)
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{
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cyg_uint32 irq_num;
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cyg_uint32 ipr, imr;
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HAL_READ_UINT32(AT91_AIC+AT91_AIC_IPR, ipr);
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HAL_READ_UINT32(AT91_AIC+AT91_AIC_IMR, imr);
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ipr &= imr;
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for (irq_num = 0; irq_num < 19; irq_num++) {
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if (ipr & (1 << irq_num)) {
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break;
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}
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}
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return irq_num;
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}
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//
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// Interrupt control
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//
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void hal_interrupt_mask(int vector)
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{
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CYG_ASSERT(vector <= CYGNUM_HAL_ISR_MAX &&
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vector >= CYGNUM_HAL_ISR_MIN , "Invalid vector");
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HAL_WRITE_UINT32(AT91_AIC+AT91_AIC_IDCR, (1<<vector));
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}
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void hal_interrupt_unmask(int vector)
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{
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CYG_ASSERT(vector <= CYGNUM_HAL_ISR_MAX &&
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vector >= CYGNUM_HAL_ISR_MIN , "Invalid vector");
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HAL_WRITE_UINT32(AT91_AIC+AT91_AIC_IECR, (1<<vector));
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}
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void hal_interrupt_acknowledge(int vector)
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{
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CYG_ASSERT(vector <= CYGNUM_HAL_ISR_MAX &&
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vector >= CYGNUM_HAL_ISR_MIN , "Invalid vector");
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HAL_WRITE_UINT32(AT91_AIC+AT91_AIC_ICCR, (1<<vector));
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// FIXME - This isn't 100% correct
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HAL_WRITE_UINT32(AT91_AIC+AT91_AIC_EOI, 0xFFFFFFFF);
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}
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void hal_interrupt_configure(int vector, int level, int up)
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{
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cyg_uint32 mode;
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CYG_ASSERT(vector <= CYGNUM_HAL_ISR_MAX &&
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vector >= CYGNUM_HAL_ISR_MIN , "Invalid vector");
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if (level) {
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if (up) {
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mode = AT91_AIC_SMR_LEVEL_HI;
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} else {
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mode = AT91_AIC_SMR_LEVEL_LOW;
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}
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} else {
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if (up) {
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mode = AT91_AIC_SMR_EDGE_POS;
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} else {
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mode = AT91_AIC_SMR_EDGE_NEG;
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}
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}
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mode |= 7; // Default priority
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HAL_WRITE_UINT32(AT91_AIC+(AT91_AIC_SMR0+(vector*4)), mode);
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}
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void hal_interrupt_set_level(int vector, int level)
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{
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cyg_uint32 mode;
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CYG_ASSERT(vector <= CYGNUM_HAL_ISR_MAX &&
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vector >= CYGNUM_HAL_ISR_MIN , "Invalid vector");
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CYG_ASSERT(level >= 1 && level <= 7, "Invalid level");
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HAL_READ_UINT32(AT91_AIC+(AT91_AIC_SMR0+(vector*4)), mode);
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mode = (mode & ~AT91_AIC_SMR_PRIORITY) | level;
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HAL_WRITE_UINT32(AT91_AIC+(AT91_AIC_SMR0+(vector*4)), mode);
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}
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void hal_show_IRQ(int vector, int data, int handler)
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{
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// UNDEFINED(__FUNCTION__); // FIXME
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}
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//
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// Diagnostic LEDs - there are three colored LEDs which can be used
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// to send a simple diagnostic value (8 bits)
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//
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void
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_at91_led(int val)
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{
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int i, to;
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HAL_WRITE_UINT32(AT91_PIO+AT91_PIO_CODR, 0x06); // DATA+CLOCK LEDs off
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for (to = 0; to < 0x200000; to++) ;
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for (i = 0; i < 8; i++) {
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HAL_WRITE_UINT32(AT91_PIO+AT91_PIO_SODR, ((val>>(7-i)) & 0x01)<<2); // DATA LED
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HAL_WRITE_UINT32(AT91_PIO+AT91_PIO_SODR, 0x02); // CLOCK LED on
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for (to = 0; to < 0x80000; to++) ;
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HAL_WRITE_UINT32(AT91_PIO+AT91_PIO_CODR, 0x02); // CLOCK LED off
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for (to = 0; to < 0x40000; to++) ;
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HAL_WRITE_UINT32(AT91_PIO+AT91_PIO_CODR, 0x04); // DATA LED off
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}
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}
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void
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set_leds(int val)
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{
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HAL_WRITE_UINT32(AT91_PIO+AT91_PIO_CODR, 0x16);
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HAL_WRITE_UINT32(AT91_PIO+AT91_PIO_SODR, val);
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}
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//--------------------------------------------------------------------------
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// EOF hal_misc.c
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