OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [rtos/] [ecos-2.0/] [packages/] [hal/] [arm/] [e7t/] [v2_0/] [include/] [hal_platform_setup.h] - Blame information for rev 631

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 27 unneback
#ifndef CYGONCE_HAL_PLATFORM_SETUP_H
2
#define CYGONCE_HAL_PLATFORM_SETUP_H
3
 
4
/*=============================================================================
5
//
6
//      hal_platform_setup.h
7
//
8
//      Platform specific support for HAL (assembly code)
9
//
10
//=============================================================================
11
//####ECOSGPLCOPYRIGHTBEGIN####
12
// -------------------------------------------
13
// This file is part of eCos, the Embedded Configurable Operating System.
14
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
15
//
16
// eCos is free software; you can redistribute it and/or modify it under
17
// the terms of the GNU General Public License as published by the Free
18
// Software Foundation; either version 2 or (at your option) any later version.
19
//
20
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
21
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
22
// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
23
// for more details.
24
//
25
// You should have received a copy of the GNU General Public License along
26
// with eCos; if not, write to the Free Software Foundation, Inc.,
27
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
28
//
29
// As a special exception, if other files instantiate templates or use macros
30
// or inline functions from this file, or you compile this file and link it
31
// with other works to produce a work based on this file, this file does not
32
// by itself cause the resulting work to be covered by the GNU General Public
33
// License. However the source code for this file must still be made available
34
// in accordance with section (3) of the GNU General Public License.
35
//
36
// This exception does not invalidate any other reasons why a work based on
37
// this file might be covered by the GNU General Public License.
38
//
39
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
40
// at http://sources.redhat.com/ecos/ecos-license/
41
// -------------------------------------------
42
//####ECOSGPLCOPYRIGHTEND####
43
//=============================================================================
44
//#####DESCRIPTIONBEGIN####
45
//
46
// Author(s):   jskov
47
// Contributors:jskov
48
// Date:        2001-03-16
49
// Purpose:     E7T platform specific support routines
50
// Description:
51
// Usage:       #include <cyg/hal/hal_platform_setup.h>
52
//
53
//####DESCRIPTIONEND####
54
//
55
//===========================================================================*/
56
 
57
#include <cyg/hal/plf_io.h>
58
 
59
#define CYGHWR_LED_MACRO                                                  \
60
        ldr     r0,=E7T_IOPDATA                                          ;\
61
        mov     r1, #((15 & (\x)) << 4)                                  ;\
62
        str     r1, [r0]                                                 ;
63
 
64
#if CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE==4096
65
// Override default to a more sensible value
66
#undef  CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE
67
#define CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE 2048
68
#endif
69
 
70
#if defined(CYG_HAL_STARTUP_ROM) || defined(CYG_HAL_STARTUP_ROMRAM)
71
#define PLATFORM_SETUP1                                                 ;\
72
        ldr     r1,=E7T_IOPMOD                                          ;\
73
        ldr     r2,=0x0001fcf0 /* set led + seg to output */            ;\
74
        str     r2,[r1,#0x00]                                           ;\
75
        ldr     r1,=E7T_IOPDATA                                         ;\
76
        ldr     r2,=0x00000050 /* set leds */                           ;\
77
        str     r2,[r1,#0x00]                                           ;\
78
                                                                        ;\
79
20:     ldr     lr,=33f                                                 ;\
80
        ldr     r0,=12f                                                 ;\
81
        ldmia   r0,{r1-r12}                                             ;\
82
        ldr     r0,=E7T_EXTDBWTH                                        ;\
83
        stmia   r0,{r1-r12}                                             ;\
84
        mov     pc,lr                                                   ;\
85
                                                                        ;\
86
        /* The below are set with a store-multiple instruction */       ;\
87
        /* Flash is 16 bit, SRAM is 32 bit */                           ;\
88
        /* .long   E7T_EXTDBWTH */                                      ;\
89
12:     .long  ( (E7T_EXTDBWTH_16BIT<<E7T_EXTDBWTH_DSR0_shift)           \
90
                |(E7T_EXTDBWTH_32BIT<<E7T_EXTDBWTH_DSR1_shift)           \
91
                |(E7T_EXTDBWTH_32BIT<<E7T_EXTDBWTH_DSR2_shift) )        ;\
92
        /* Flash at 0x01800000-0x01880000, 5 cycles, 4 cycles */        ;\
93
        /* .long   E7T_ROMCON0 */                                       ;\
94
        .long  ( (E7T_ROMCON_PMC_ROM)                                    \
95
                |(E7T_ROMCON_TPA_5C)                                     \
96
                |(E7T_ROMCON_TACC_4C)                                    \
97
                |((0x01800000 >> 16) << E7T_ROMCON_BASE_shift)           \
98
                |((0x01880000 >> 16) << E7T_ROMCON_NEXT_shift))         ;\
99
        /* SRAM at 0x00000000-0x00400000, 5 cycles, 2 cycles */         ;\
100
        /* .long   E7T_ROMCON1 */                                       ;\
101
        .long  ( (E7T_ROMCON_PMC_ROM)                                    \
102
                |(E7T_ROMCON_TPA_5C)                                     \
103
                |(E7T_ROMCON_TACC_2C)                                    \
104
                |((0x00000000 >> 16) << E7T_ROMCON_BASE_shift)           \
105
                |((0x00040000 >> 16) << E7T_ROMCON_NEXT_shift))         ;\
106
        /* SRAM at 0x00400000-0x00800000, 5 cycles, 2 cycles */         ;\
107
        /* .long   E7T_ROMCON2 */                                       ;\
108
        .long  ( (E7T_ROMCON_PMC_ROM)                                    \
109
                |(E7T_ROMCON_TPA_5C)                                     \
110
                |(E7T_ROMCON_TACC_2C)                                    \
111
                |((0x00040000 >> 16) << E7T_ROMCON_BASE_shift)           \
112
                |((0x00080000 >> 16) << E7T_ROMCON_NEXT_shift))         ;\
113
        /* Below values are what Boot Monitor sets up */                ;\
114
        /* .long   E7T_ROMCON3 */                                       ;\
115
        .long   0x08018020                                              ;\
116
        /* .long   E7T_ROMCON4 */                                       ;\
117
        .long   0x0a020040                                              ;\
118
        /* .long   E7T_ROMCON5 */                                       ;\
119
        .long   0x0c028040                                              ;\
120
        /* .long   E7T_DRAMCON0 */                                      ;\
121
        .long   0x00000000                                              ;\
122
        /* .long   E7T_DRAMCON1 */                                      ;\
123
        .long   0x00000000                                              ;\
124
        /* .long   E7T_DRAMCON2 */                                      ;\
125
        .long   0x00000000                                              ;\
126
        /* .long   E7T_DRAMCON3 */                                      ;\
127
        .long   0x00000000                                              ;\
128
        /* .long   E7T_REFEXTCON */                                     ;\
129
        .long   0x9c218360                                              ;\
130
                                                                        ;\
131
33:
132
#else
133
#define PLATFORM_SETUP1
134
#endif
135
 
136
//-----------------------------------------------------------------------------
137
// end of hal_platform_setup.h
138
#endif // CYGONCE_HAL_PLATFORM_SETUP_H

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.