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[/] [openrisc/] [trunk/] [rtos/] [ecos-2.0/] [packages/] [hal/] [arm/] [e7t/] [v2_0/] [src/] [e7t_misc.c] - Blame information for rev 174

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//==========================================================================
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//
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//      e7t_misc.c
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//
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//      HAL misc board support code for ARM E7T
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//
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//==========================================================================
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//####ECOSGPLCOPYRIGHTBEGIN####
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// -------------------------------------------
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// This file is part of eCos, the Embedded Configurable Operating System.
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// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
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//
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// eCos is free software; you can redistribute it and/or modify it under
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// the terms of the GNU General Public License as published by the Free
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// Software Foundation; either version 2 or (at your option) any later version.
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//
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// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or
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// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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// for more details.
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//
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// You should have received a copy of the GNU General Public License along
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// with eCos; if not, write to the Free Software Foundation, Inc.,
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// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
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//
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// As a special exception, if other files instantiate templates or use macros
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// or inline functions from this file, or you compile this file and link it
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// with other works to produce a work based on this file, this file does not
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// by itself cause the resulting work to be covered by the GNU General Public
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// License. However the source code for this file must still be made available
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// in accordance with section (3) of the GNU General Public License.
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//
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// This exception does not invalidate any other reasons why a work based on
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// this file might be covered by the GNU General Public License.
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//
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// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
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// at http://sources.redhat.com/ecos/ecos-license/
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// -------------------------------------------
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//####ECOSGPLCOPYRIGHTEND####
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//==========================================================================
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//#####DESCRIPTIONBEGIN####
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//
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// Author(s):    gthomas
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// Contributors: gthomas, jskov
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// Date:         2001-03-16
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// Purpose:      HAL board support
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// Description:  Implementations of HAL board interfaces
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//
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//####DESCRIPTIONEND####
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//
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//========================================================================*/
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#include <pkgconf/hal.h>
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#include <cyg/infra/cyg_type.h>         // base types
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#include <cyg/infra/cyg_trac.h>         // tracing macros
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#include <cyg/infra/cyg_ass.h>          // assertion macros
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#include <cyg/hal/hal_io.h>             // IO macros
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#include <cyg/hal/hal_arch.h>           // Register state info
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#include <cyg/hal/hal_diag.h>
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#include <cyg/hal/hal_intr.h>           // necessary?
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#include <cyg/hal/hal_cache.h>
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#include <cyg/hal/hal_if.h>             // calling interface
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#include <cyg/hal/hal_misc.h>           // helper functions
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#ifdef CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT
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#include <cyg/hal/drv_api.h>            // HAL ISR support
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#endif
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#include <cyg/hal/plf_io.h>             // platform registers
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static cyg_uint32 _period;
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#ifdef CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT
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static cyg_interrupt abort_interrupt;
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static cyg_handle_t  abort_interrupt_handle;
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// This ISR is called only for the Abort button interrupt
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static int
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e7t_abort_isr(cyg_vector_t vector, cyg_addrword_t data, HAL_SavedRegisters *regs)
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{
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    cyg_hal_user_break((CYG_ADDRWORD*)regs);
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    cyg_drv_interrupt_acknowledge(CYGNUM_HAL_INTERRUPT_EXT0);
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    return 0;  // No need to run DSR
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}
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#endif
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void hal_clock_initialize(cyg_uint32 period)
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{
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    cyg_uint32 tmod;
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    // Disable timer 0
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    HAL_READ_UINT32(E7T_TMOD, tmod);
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    tmod &= ~(E7T_TMOD_TE0);
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    HAL_WRITE_UINT32(E7T_TMOD, 0);
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    tmod &= ~(E7T_TMOD_TMD0 | E7T_TMOD_TCLR0);
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    tmod |= E7T_TMOD_TE0;
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    // Set counter
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    HAL_WRITE_UINT32(E7T_TDATA0, period);
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    // And enable timer
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    HAL_WRITE_UINT32(E7T_TMOD, tmod);
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    _period = period;
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#ifdef CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT
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    cyg_drv_interrupt_create(CYGNUM_HAL_INTERRUPT_EXT0,
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                             99,           // Priority
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                             0,            // Data item passed to interrupt handler
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                             e7t_abort_isr,
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                             0,
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                             &abort_interrupt_handle,
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                             &abort_interrupt);
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    cyg_drv_interrupt_attach(abort_interrupt_handle);
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    cyg_drv_interrupt_unmask(CYGNUM_HAL_INTERRUPT_EXT0);
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#endif
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}
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void hal_clock_reset(cyg_uint32 vector, cyg_uint32 period)
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{
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    _period = period;
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}
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void hal_clock_read(cyg_uint32 *pvalue)
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{
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    cyg_uint32 value;
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    HAL_READ_UINT32(E7T_TCNT0, value);
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    *pvalue = _period - value;
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}
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// -------------------------------------------------------------------------
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//
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// Delay for some number of micro-seconds
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//
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void hal_delay_us(cyg_int32 usecs)
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{
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    cyg_uint32 count;
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    cyg_uint32 ticks = ((CYGNUM_HAL_RTC_PERIOD*CYGNUM_HAL_RTC_DENOMINATOR)/1000000) * usecs;
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    cyg_uint32 tmod;
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    // Disable timer 1
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    HAL_READ_UINT32(E7T_TMOD, tmod);
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    tmod &= ~(E7T_TMOD_TE1);
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    HAL_WRITE_UINT32(E7T_TMOD, tmod);
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    tmod &= ~(E7T_TMOD_TMD1 | E7T_TMOD_TCLR1);
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    tmod |= E7T_TMOD_TE1;
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    // Clear pending flag
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    HAL_WRITE_UINT32(E7T_INTPND, (1 << CYGNUM_HAL_INTERRUPT_TIMER1));
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    // Set counter
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    HAL_WRITE_UINT32(E7T_TDATA1, ticks);
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    // And enable timer
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    HAL_WRITE_UINT32(E7T_TMOD, tmod);
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    // Wait for timer to underflow. Can't test the timer completion
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    // bit without actually enabling the interrupt. So instead watch
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    // the counter.
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    ticks /= 2;                         // wait for this threshold
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    // Wait till timer counts below threshold
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    do {
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        HAL_READ_UINT32(E7T_TCNT1, count);
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    } while (count >= ticks);
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    // then wait for it to be reloaded
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    do {
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        HAL_READ_UINT32(E7T_TCNT1, count);
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    } while (count < ticks);
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    // Then disable timer 1 again
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    tmod &= ~E7T_TMOD_TE1;
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    HAL_WRITE_UINT32(E7T_TMOD, tmod);
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}
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// -------------------------------------------------------------------------
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// Hardware init
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void hal_hardware_init(void)
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{
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    cyg_uint32 intmask;
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    // Set up eCos/ROM interfaces
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    hal_if_init();
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    // Enable cache
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    HAL_WRITE_UINT32(E7T_SYSCFG,
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                     0x07FFFF80|E7T_SYSCFG_CM_0R_8C|E7T_SYSCFG_WE);
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    HAL_UCACHE_INVALIDATE_ALL();
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    HAL_UCACHE_ENABLE();
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    // Clear global interrupt mask bit
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    HAL_READ_UINT32(E7T_INTMSK, intmask);
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    intmask &= ~E7T_INTMSK_GLOBAL;
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    HAL_WRITE_UINT32(E7T_INTMSK, intmask);
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}
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//
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// This routine is called to respond to a hardware interrupt (IRQ).  It
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// should interrogate the hardware and return the IRQ vector number.
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int hal_IRQ_handler(void)
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{
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    // Do hardware-level IRQ handling
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    cyg_uint32 irq_status;
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    HAL_READ_UINT32(E7T_INTOFFSET_IRQ, irq_status);
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    irq_status = irq_status / 4;
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    if (CYGNUM_HAL_ISR_MAX >= irq_status)
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        return irq_status;
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    // It's a bit bogus to test for FIQs after IRQs, but we use the
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    // latter more, so don't impose the overhead of checking for FIQs
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    HAL_READ_UINT32(E7T_INTOFFSET_FIQ, irq_status);
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    irq_status = irq_status / 4;
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    if (CYGNUM_HAL_ISR_MAX >= irq_status)
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        return irq_status;
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    return CYGNUM_HAL_INTERRUPT_NONE;
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}
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//
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// Interrupt control
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//
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void hal_interrupt_mask(int vector)
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{
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    cyg_uint32 mask, old_mask;
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    HAL_READ_UINT32(E7T_INTMSK, mask);
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    old_mask = mask;
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    mask |= (1<<vector);
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    HAL_WRITE_UINT32(E7T_INTMSK, mask);
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}
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void hal_interrupt_unmask(int vector)
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{
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    cyg_uint32 mask, old_mask;
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    HAL_READ_UINT32(E7T_INTMSK, mask);
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    old_mask = mask;
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    mask &= ~(1<<vector);
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    HAL_WRITE_UINT32(E7T_INTMSK, mask);
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}
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void hal_interrupt_acknowledge(int vector)
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{
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    HAL_WRITE_UINT32(E7T_INTPND, (1<<vector));
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}
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void hal_interrupt_configure(int vector, int level, int up)
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{
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}
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void hal_interrupt_set_level(int vector, int level)
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{
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}
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void hal_show_IRQ(int vector, int data, int handler)
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{
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}
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//--------------------------------------------------------------------------
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// EOF hal_misc.c

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