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#ifndef CYGONCE_PLF_IO_H
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#define CYGONCE_PLF_IO_H
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//=============================================================================
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//
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// plf_io.h
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//
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// Platform specific IO support
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//
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//=============================================================================
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//####ECOSGPLCOPYRIGHTBEGIN####
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// -------------------------------------------
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// This file is part of eCos, the Embedded Configurable Operating System.
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// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
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//
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// eCos is free software; you can redistribute it and/or modify it under
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// the terms of the GNU General Public License as published by the Free
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// Software Foundation; either version 2 or (at your option) any later version.
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//
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// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// for more details.
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//
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// You should have received a copy of the GNU General Public License along
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// with eCos; if not, write to the Free Software Foundation, Inc.,
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// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
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//
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// As a special exception, if other files instantiate templates or use macros
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// or inline functions from this file, or you compile this file and link it
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// with other works to produce a work based on this file, this file does not
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// by itself cause the resulting work to be covered by the GNU General Public
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// License. However the source code for this file must still be made available
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// in accordance with section (3) of the GNU General Public License.
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//
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// This exception does not invalidate any other reasons why a work based on
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// this file might be covered by the GNU General Public License.
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//
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// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
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// at http://sources.redhat.com/ecos/ecos-license/
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// -------------------------------------------
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//####ECOSGPLCOPYRIGHTEND####
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//=============================================================================
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//#####DESCRIPTIONBEGIN####
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//
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// Author(s): hmt, jskov
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// Contributors: hmt, jskov
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// Date: 1999-08-09
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// Purpose: Intel EBSA285 PCI IO support macros
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// Description:
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// Usage: #include <cyg/hal/plf_io.h>
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//
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// Note: Based on information in
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// "21285 Core Logic for SA-110 Microprocessor"
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//####DESCRIPTIONEND####
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//
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//=============================================================================
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#include <pkgconf/hal_arm_ebsa285.h>
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#include <cyg/hal/hal_ebsa285.h>
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#include <cyg/hal/hal_io.h> // IO macros
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#include <cyg/hal/hal_platform_ints.h> // Interrupt vectors
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// Memory map is 1-1
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#define CYGARC_PHYSICAL_ADDRESS(_x_) (_x_)
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// The PCI resources required by the EBSA are hardcoded to the lowest
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// addresses in the PCI address space, thus:
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// PCI Memory Space
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#define EBSA_SDRAM_PCI_ADDR 0
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#define EBSA_SDRAM_PCI_SIZE (CYGHWR_HAL_ARM_EBSA285_PCI_MEM_MAP_SIZE)
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#define EBSA_CSR_MEM_PCI_ADDR (EBSA_SDRAM_PCI_SIZE)
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#define EBSA_CSR_MEM_PCI_SIZE 0x80
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// PCI IO Space
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#define EBSA_CSR_IO_PCI_ADDR 0
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#define EBSA_CSR_IO_PCI_SIZE 0x80
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// Incidentally I now understand why it's necessary to force PCI reset
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// (2000-08-07) - with RedBoot in ROM, the RAM app was unconditionally
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// reinitializing the PCI bus when it was already initialized, without
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// resetting it. We cannot play the same game here as with
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// hal_platform_setup.h - I tried - because otherwise the net cannot
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// re-initialize itself; the scan for devices fails.
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// Initialize the PCI bus.
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#define HAL_PCI_INIT() \
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CYG_MACRO_START \
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cyg_uint32 __tmp, __tmp2; \
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\
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/* Assert PCI_reset */ \
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HAL_READ_UINT32(SA110_CONTROL, __tmp); \
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__tmp &= ~SA110_CONTROL_RST_I; \
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HAL_WRITE_UINT32(SA110_CONTROL, __tmp); \
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\
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/* Disable PCI Outbound interrupts */ \
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/* (according to 7-14 SA110_OUT_INT_MASK is not accessible */ \
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/* by SA-100) */ \
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HAL_WRITE_UINT32(SA110_OUT_INT_STATUS, \
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SA110_OUT_INT_STATUS_DOORBELL_INT \
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|SA110_OUT_INT_STATUS_OUTBOUND_INT); \
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\
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/* Disable Doorbells */ \
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HAL_WRITE_UINT32(SA110_DOORBELL_PCI_MASK, 0); \
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HAL_WRITE_UINT32(SA110_DOORBELL_SA_MASK, 0); \
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\
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/* Map high PCI address bits to 0 */ \
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HAL_WRITE_UINT32(SA110_PCI_ADDR_EXT, 0); \
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\
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/* Interrupt ID to 1 */ \
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HAL_WRITE_UINT16(SA110_PCI_CFG_INT_LINE, 0x0100); \
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\
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/* Remove PCI_reset */ \
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HAL_READ_UINT32(SA110_CONTROL, __tmp); \
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__tmp |= SA110_CONTROL_RST_I; \
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HAL_WRITE_UINT32(SA110_CONTROL, __tmp); \
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\
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/* Open a window to SDRAM from PCI address space */ \
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HAL_WRITE_UINT32(SA110_SDRAM_BASE_ADDRESS_MASK, \
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((CYGHWR_HAL_ARM_EBSA285_PCI_MEM_MAP_SIZE-1) & 0xfffc0000)); \
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HAL_WRITE_UINT32(SA110_SDRAM_BASE_ADDRESS_OFFSET, \
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CYGHWR_HAL_ARM_EBSA285_PCI_MEM_MAP_BASE); \
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\
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/* Only init PCI if central function is set and */ \
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/* standalone bit is cleared */ \
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HAL_READ_UINT32(SA110_CONTROL, __tmp); \
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HAL_READ_UINT32(SA110_XBUS_XCS2, __tmp2); \
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if ((__tmp & SA110_CONTROL_CFN) == SA110_CONTROL_CFN \
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&& (__tmp2 & SA110_XBUS_XCS2_PCI_DISABLE) == 0) { \
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\
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/* Don't respond to any commands */ \
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HAL_WRITE_UINT16(SA110_PCI_CFG_COMMAND, 0); \
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\
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/* Set up default addresses for board's resources. */ \
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HAL_WRITE_UINT32(SA110_PCI_CFG_CSR_MEM_BAR, \
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EBSA_CSR_MEM_PCI_ADDR); \
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HAL_WRITE_UINT32(SA110_PCI_CFG_CSR_IO_BAR, EBSA_CSR_IO_PCI_ADDR);\
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HAL_WRITE_UINT32(SA110_PCI_CFG_SDRAM_BAR, EBSA_SDRAM_PCI_ADDR); \
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\
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/* Respond to I/O space & Memory transactions. */ \
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HAL_WRITE_UINT32(SA110_PCI_CFG_COMMAND, \
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CYG_PCI_CFG_COMMAND_INVALIDATE \
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|CYG_PCI_CFG_COMMAND_IO \
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|CYG_PCI_CFG_COMMAND_MEMORY \
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|CYG_PCI_CFG_COMMAND_MASTER); \
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} \
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/* Signal PCI_init_complete */ \
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HAL_READ_UINT32(SA110_CONTROL, __tmp); \
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__tmp |= SA110_CONTROL_INIT_COMPLETE; \
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HAL_WRITE_UINT32(SA110_CONTROL, __tmp); \
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\
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CYG_MACRO_END
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// Compute address necessary to access PCI config space for the given
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// bus and device.
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#define HAL_PCI_CONFIG_ADDRESS( __bus, __devfn, __offset ) \
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({ \
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cyg_uint32 __addr; \
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cyg_uint32 __dev = CYG_PCI_DEV_GET_DEV(__devfn); \
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if (0 == __bus) { \
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if (0 == __dev) { \
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/* Access self via CSR base */ \
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__addr = SA110_CONTROL_STATUS_BASE; \
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} else { \
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/* Page 3-17, table 3-5: bits 15-11 generate PCI address */ \
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__addr = SA110_PCI_CONFIG0_BASE | 0x00c00000 | (__dev << 11);\
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} \
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} else { \
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__addr = SA110_PCI_CONFIG1_BASE | (__bus << 16) | (__dev << 11); \
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} \
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__addr |= CYG_PCI_DEV_GET_FN(__devfn) << 8; \
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__addr |= __offset; \
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__addr; \
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})
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// Read a value from the PCI configuration space of the appropriate
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// size at an address composed from the bus, devfn and offset.
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#define HAL_PCI_CFG_READ_UINT8( __bus, __devfn, __offset, __val ) \
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HAL_READ_UINT8(HAL_PCI_CONFIG_ADDRESS(__bus, __devfn, __offset), __val)
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#define HAL_PCI_CFG_READ_UINT16( __bus, __devfn, __offset, __val ) \
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HAL_READ_UINT16(HAL_PCI_CONFIG_ADDRESS(__bus, __devfn, __offset), __val)
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#define HAL_PCI_CFG_READ_UINT32( __bus, __devfn, __offset, __val ) \
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HAL_READ_UINT32(HAL_PCI_CONFIG_ADDRESS(__bus, __devfn, __offset), __val)
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// Write a value to the PCI configuration space of the appropriate
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// size at an address composed from the bus, devfn and offset.
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#define HAL_PCI_CFG_WRITE_UINT8( __bus, __devfn, __offset, __val ) \
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HAL_WRITE_UINT8(HAL_PCI_CONFIG_ADDRESS(__bus, __devfn, __offset), __val)
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#define HAL_PCI_CFG_WRITE_UINT16( __bus, __devfn, __offset, __val ) \
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HAL_WRITE_UINT16(HAL_PCI_CONFIG_ADDRESS(__bus, __devfn, __offset), __val)
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#define HAL_PCI_CFG_WRITE_UINT32( __bus, __devfn, __offset, __val ) \
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HAL_WRITE_UINT32(HAL_PCI_CONFIG_ADDRESS(__bus, __devfn, __offset), __val)
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//-----------------------------------------------------------------------------
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// Resources
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// Map PCI device resources starting from these addresses in PCI space.
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#define HAL_PCI_ALLOC_BASE_MEMORY (EBSA_SDRAM_PCI_SIZE+EBSA_CSR_MEM_PCI_SIZE)
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#define HAL_PCI_ALLOC_BASE_IO (EBSA_CSR_IO_PCI_SIZE)
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// This is where the PCI spaces are mapped in the CPU's address space.
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#define HAL_PCI_PHYSICAL_MEMORY_BASE 0x80000000
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#define HAL_PCI_PHYSICAL_IO_BASE 0x7c000000
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// Translate the PCI interrupt requested by the device (INTA#, INTB#,
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// INTC# or INTD#) to the associated CPU interrupt (i.e., HAL vector).
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#define HAL_PCI_TRANSLATE_INTERRUPT( __bus, __devfn, __vec, __valid) \
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CYG_MACRO_START \
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cyg_uint8 __req; \
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HAL_PCI_CFG_READ_UINT8(__bus, __devfn, CYG_PCI_CFG_INT_PIN, __req); \
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if (0 != __req) { \
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/* Interrupt assignment as 21285 sees them. (From */ \
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/* EBSA285 Eval Board Reference Manual, 3.4 Interrupt Assignment) */ \
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CYG_ADDRWORD __translation[4] = { \
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CYGNUM_HAL_INTERRUPT_IRQ_IN_1, /* INTC# */ \
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CYGNUM_HAL_INTERRUPT_IRQ_IN_0, /* INTB# */ \
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CYGNUM_HAL_INTERRUPT_PCI_IRQ, /* INTA# */ \
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CYGNUM_HAL_INTERRUPT_IRQ_IN_3}; /* INTD# */ \
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\
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/* The PCI lines from the different slots are wired like this */ \
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/* on the PCI backplane: */ \
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/* pin6A pin7B pin7A pin8B */ \
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/* System Slot INTA# INTB# INTC# INTD# */ \
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/* I/O Slot 1 INTB# INTC# INTD# INTA# */ \
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/* I/O Slot 2 INTC# INTD# INTA# INTB# */ \
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/* I/O Slot 3 INTD# INTA# INTB# INTC# */ \
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/* I/O Slot 4 INTA# INTB# INTC# INTD# */ \
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/* */ \
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/* (From PCI Development Backplane, 3.2.2 Interrupts) */ \
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/* */ \
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/* Devsel signals are wired to, resulting in device IDs: */ \
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/* I/O Slot 1 AD19 / dev 8 [(8+1)&3 = 1] */ \
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/* I/O Slot 2 AD18 / dev 7 [(7+1)&3 = 0] */ \
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/* I/O Slot 3 AD17 / dev 6 [(6+1)&3 = 3] */ \
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/* I/O Slot 4 AD16 / dev 5 [(5+1)&3 = 2] */ \
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/* */ \
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/* (From PCI Development Backplane, 3.2.1 General) */ \
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/* */ \
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/* The observant reader will notice that the array does not */ \
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/* match the table of how interrupts are wired. The array */ \
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/* does however match observed behavior of the hardware: */ \
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/* */ \
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/* Observed interrupts with an Intel ethernet card */ \
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/* put in the slots in turn and set to generate interrupts: */ \
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/* slot 1/intA# (dev 8): caused host INTB# */ \
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/* slot 2/intA# (dev 7): caused host INTC# */ \
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/* slot 3/intA# (dev 6): caused host INTD# */ \
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/* slot 4/intA# (dev 5): caused host INTA# */ \
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\
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__vec = __translation[((__req+CYG_PCI_DEV_GET_DEV(__devfn))&3)]; \
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__valid = true; \
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} else { \
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/* Device will not generate interrupt requests. */ \
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__valid = false; \
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} \
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CYG_MACRO_END
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//-----------------------------------------------------------------------------
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// end of plf_io.h
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#endif // CYGONCE_PLF_IO_H
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