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#ifndef CYGONCE_HAL_PLATFORM_SETUP_H
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#define CYGONCE_HAL_PLATFORM_SETUP_H
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/*=============================================================================
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//
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// hal_platform_setup.h
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//
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// Platform specific support for HAL (assembly code)
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//
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//=============================================================================
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//####ECOSGPLCOPYRIGHTBEGIN####
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// -------------------------------------------
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// This file is part of eCos, the Embedded Configurable Operating System.
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// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
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// Copyright (C) 2003 Gary Thomas <gary@mind.be>
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//
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// eCos is free software; you can redistribute it and/or modify it under
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// the terms of the GNU General Public License as published by the Free
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// Software Foundation; either version 2 or (at your option) any later version.
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//
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// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// for more details.
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//
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// You should have received a copy of the GNU General Public License along
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// with eCos; if not, write to the Free Software Foundation, Inc.,
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// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
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//
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// As a special exception, if other files instantiate templates or use macros
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// or inline functions from this file, or you compile this file and link it
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// with other works to produce a work based on this file, this file does not
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// by itself cause the resulting work to be covered by the GNU General Public
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// License. However the source code for this file must still be made available
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// in accordance with section (3) of the GNU General Public License.
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//
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// This exception does not invalidate any other reasons why a work based on
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// this file might be covered by the GNU General Public License.
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//
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// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
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// at http://sources.redhat.com/ecos/ecos-license/
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// -------------------------------------------
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//####ECOSGPLCOPYRIGHTEND####
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//=============================================================================
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//#####DESCRIPTIONBEGIN####
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//
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// Author(s): gthomas
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// Contributors: gthomas
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// Date: 1999-04-21
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// Purpose: Cirrus EDB7XXX platform specific support routines
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// Description:
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// Usage: #include <cyg/hal/hal_platform_setup.h>
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//
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//####DESCRIPTIONEND####
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//
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//===========================================================================*/
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#include <pkgconf/system.h> // System-wide configuration info
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#include <pkgconf/hal.h> // Architecture independent configuration
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#include CYGBLD_HAL_PLATFORM_H // Platform specific configuration
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#include <cyg/hal/hal_edb7xxx.h> // Platform specific hardware definitions
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#include <cyg/hal/hal_mmu.h> // MMU definitions
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#define CYGHWR_HAL_ARM_HAS_MMU // This processor has an MMU
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#define CYGSEM_HAL_ROM_RESET_USES_JUMP
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//
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// Memory map - set up by ROM (GDB stubs)
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//
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// Region Logical Address Physical Address
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// DRAM 0x00000000..0x00xFFFFF 0xC00x0000 (see below)
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// Expansion 2 0x20000000 0x20000000
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// Expansion 3 0x30000000 0x30000000
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// PCMCIA 0 0x40000000 0x40000000
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// PCMCIA 1 0x50000000 0x50000000
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// SRAM 0x60000000..0x600007FF 0x60000000
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// I/O 0x80000000 0x80000000
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// MMU Tables 0xC00y0000
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// LCD buffer 0xC0000000..0xC001FFFF 0xC0000000
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// ROM 0xE0000000..0xEFFFFFFF 0x00000000
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// ROM 0xF0000000..0xFFFFFFFF 0x10000000
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#ifdef CYGHWR_HAL_ARM_EDB7XXX_LCD_INSTALLED
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#define LCD_BUFFER_SIZE 0x00020000
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#else
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#define LCD_BUFFER_SIZE 0x00000000
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#endif
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#define DRAM_PA_START 0xC0000000
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#define MMU_BASE DRAM_PA_START+LCD_BUFFER_SIZE
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#define PTE_BASE MMU_BASE+0x4000
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#if (CYGHWR_HAL_ARM_EDB7XXX_DRAM_SIZE == 2)
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#define MMU_TABLES_SIZE (0x4000+0x1000+0x1000) // RAM used for PTE entries
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#define DRAM_LA_END (0x00200000-MMU_TABLES_SIZE-LCD_BUFFER_SIZE)
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#elif (CYGHWR_HAL_ARM_EDB7XXX_DRAM_SIZE == 16)
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#define MMU_TABLES_SIZE (0x4000+0x4000+0x1000) // RAM used for PTE entries
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#define DRAM_LA_END (0x01000000-MMU_TABLES_SIZE-LCD_BUFFER_SIZE)
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#endif
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#define DRAM_LA_START 0x00000000
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#define DRAM_PA MMU_BASE+MMU_TABLES_SIZE
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#define LCD_LA_START 0xC0000000
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#define LCD_LA_END 0xC0020000
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#define LCD_PA 0xC0000000
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#define ROM0_LA_START 0xE0000000
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#define ROM0_PA 0x00000000
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#define ROM0_LA_END 0xF0000000
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#define ROM1_LA_START 0xF0000000
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#define ROM1_LA_END 0x00000000
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#define ROM1_PA 0x10000000
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#define EXPANSION2_LA_START 0x20000000
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#define EXPANSION2_PA 0x20000000
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#define EXPANSION3_LA_START 0x30000000
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#define EXPANSION3_PA 0x30000000
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#define PCMCIA0_LA_START 0x40000000
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#define PCMCIA0_PA 0x40000000
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#define PCMCIA1_LA_START 0x50000000
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#define PCMCIA1_PA 0x50000000
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#define SRAM_LA_START 0x60000000
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#ifdef CYGHWR_HAL_ARM_EDB7XXX_VARIANT_CL_PS7111 // 4K SRAM
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#define SRAM_LA_END 0x60001000
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#else // 72xx - 37.5K SRAM
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#define SRAM_LA_END 0x6000A000
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#endif
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#define SRAM_PA 0x60000000
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#define IO_LA_START 0x80000000
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#define IO_LA_END 0x8000f000
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#define IO_PA 0x80000000
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#ifndef _CYGHWR_LAYOUT_ONLY
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// Define startup code [macros]
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#if defined(CYGSEM_HAL_INSTALL_MMU_TABLES)
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#ifdef CYGHWR_HAL_ARM_EDB7XXX_VARIANT_CL_PS7111 // CL7111, 710 processor
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.macro MMU_INITIALIZE
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ldr r2,=MMU_Control_Init
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mcr MMU_CP,0,r2,MMU_Control,c0 /* MMU off */
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mcr MMU_CP,0,r1,MMU_Base,c0
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mcr MMU_CP,0,r1,MMU_FlushTLB,c0,0 /* Invalidate TLB */
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mcr MMU_CP,0,r1,MMU_FlushIDC,c0,0 /* Invalidate Caches */
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ldr r1,=0xFFFFFFFF
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mcr MMU_CP,0,r1,MMU_DomainAccess,c0
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ldr r2,=10f
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ldr r1,=MMU_Control_Init|MMU_Control_M
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mcr MMU_CP,0,r1,MMU_Control,c0
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mov pc,r2 /* Change address spaces */
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nop
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nop
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nop
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10:
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.endm
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#else // EP7xxx, 720T processor
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.macro MMU_INITIALIZE
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ldr r2,=MMU_Control_Init
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mcr MMU_CP,0,r2,MMU_Control,c0 /* MMU off */
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mcr MMU_CP,0,r1,MMU_Base,c0
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mcr MMU_CP,0,r1,MMU_TLB,c7,0 /* Invalidate TLB */
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mcr MMU_CP,0,r1,MMU_FlushIDC,c0,0 /* Invalidate Caches */
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ldr r1,=0xFFFFFFFF
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mcr MMU_CP,0,r1,MMU_DomainAccess,c0
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ldr r2,=10f
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#ifdef CYG_HAL_STARTUP_ROMRAM
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ldr r3,=__exception_handlers
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sub r2,r2,r3
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ldr r3,=ROM0_LA_START
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add r2,r2,r3
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#endif
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ldr r1,=MMU_Control_Init|MMU_Control_M
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mcr MMU_CP,0,r1,MMU_Control,c0
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mov pc,r2 /* Change address spaces */
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nop
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nop
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nop
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10:
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.endm
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#endif // EP7xxx,720T processor
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#ifdef CYG_HAL_STARTUP_ROMRAM
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.macro RELOCATE_TEXT_SEGMENT
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ldr r2,=__exception_handlers
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ldr r3,=ROM0_LA_START
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cmp r2,r3
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beq 20f
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ldr r4,=__rom_data_end
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15:
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ldr r0,[r3],#4
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str r0,[r2],#4
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cmp r2,r4
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bne 15b
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ldr r2,=20f
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mov pc,r2 /* Change address spaces */
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nop
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nop
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nop
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20:
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.endm
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#endif
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#ifdef CYG_HAL_STARTUP_RAM
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.macro RELOCATE_RAM_IMAGE
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// Special code to handle case where program has been loaded into DRAM
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// _somewhere_. This code first relocates itself into DRAM where eCos
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// mapping will expect it to be. Note since we don't know the current
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// MMU mapping, this is tricky. This is handled by putting a small
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// routine into SRAM (which is always mapped 1-1) that turns off the
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// MMU whilst it stores one word into physical memory. Once the whole
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// program has been relocated thusly, the MMU is shut off again while
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// the eCos memory mapping takes place
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bl 5f
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// Routine to store one item in physical memory, with the MMU off
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_phys_store:
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ldr r5,=MMU_Control_Init
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mcr MMU_CP,0,r5,MMU_Control,c0 /* MMU off */
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nop
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nop
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nop
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mcr MMU_CP,0,r1,MMU_TLB,c7,0 /* Invalidate TLB */
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mcr MMU_CP,0,r1,MMU_FlushIDC,c0,0 /* Invalidate Caches */
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str r4,[r2],#4
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ldr r5,=MMU_Control_Init|MMU_Control_M
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mcr MMU_CP,0,r5,MMU_Control,c0
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mov pc,lr
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_phys_store_end:
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// Copy above routine to SRAM, whose address does not change with MMU
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5: mov r1,lr
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add r2,r1,#_phys_store_end-_phys_store
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ldr r3,=SRAM_LA_START
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6: ldr r4,[r1],#4
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str r4,[r3],#4
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cmp r1,r2
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bne 6b
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ldr r6,=SRAM_LA_START
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// Relocate code in DRAM to where eCos mapping wants it
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bl 7f
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7: mov r2,lr
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ldr r1,=7b
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sub r1,r2,r1
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ldr r2,=__exception_handlers
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| 236 |
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add r1,r1,r2
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| 237 |
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// ldr r1,=0xF0020000
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| 238 |
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ldr r3,=DRAM_PA
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| 239 |
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add r2,r2,r3
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| 240 |
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// ldr r2,=DRAM_PA+0x20000
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| 241 |
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ldr r3,=_edata
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| 242 |
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ldr r4,=__exception_handlers
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| 243 |
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sub r3,r3,r4
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| 244 |
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add r3,r1,r3
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| 245 |
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// ldr r3,=0xF0040000
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| 246 |
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10: ldr r4,[r1],#4
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| 247 |
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mov lr,pc // Call phys_store() function above
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| 248 |
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mov pc,r6
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| 249 |
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cmp r1,r3
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| 250 |
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bne 10b
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| 251 |
|
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// Now, turn off the MMU an execute the rest of this code in PHYSICAL memory
|
| 252 |
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ldr r1,=15f
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| 253 |
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ldr r2,=DRAM_PA
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| 254 |
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add r1,r1,r2
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| 255 |
|
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ldr r5,=MMU_Control_Init
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| 256 |
|
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mcr MMU_CP,0,r5,MMU_Control,c0 /* MMU off */
|
| 257 |
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mov pc,r1
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| 258 |
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nop
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| 259 |
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nop
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| 260 |
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nop
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| 261 |
|
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15: mcr MMU_CP,0,r1,MMU_TLB,c7,0 /* Invalidate TLB */
|
| 262 |
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mcr MMU_CP,0,r1,MMU_FlushIDC,c0,0 /* Invalidate Caches */
|
| 263 |
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.endm
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| 264 |
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#endif // CYG_HAL_STARTUP_RAM
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| 265 |
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|
| 266 |
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#ifdef CYGHWR_HAL_ARM_EDB7XXX_VARIANT_EP7312
|
| 267 |
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.macro INIT_MEMORY_CONFIG
|
| 268 |
|
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mov r0,#(CPSR_IRQ_DISABLE|CPSR_FIQ_DISABLE|CPSR_SUPERVISOR_MODE)
|
| 269 |
|
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msr cpsr,r0
|
| 270 |
|
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ldr r10,=UARTDR1
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| 271 |
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ldr r11,=SYSFLG1
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| 272 |
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ldr r12,=SYSFLG1_UTXFF1
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| 273 |
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ldr r1,=SDCONF
|
| 274 |
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ldr r2,=0x00000522
|
| 275 |
|
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str r2,[r1]
|
| 276 |
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ldr r1,=SDRFOR
|
| 277 |
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ldr r2,=0x00000240
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| 278 |
|
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str r2,[r1]
|
| 279 |
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ldr r1,=MEMCFG1
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| 280 |
|
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ldr r2,=0x1F101710
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| 281 |
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str r2,[r1]
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| 282 |
|
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ldr r1,=MEMCFG2
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| 283 |
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ldr r2,=0x00001F13
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| 284 |
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str r2,[r1]
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| 285 |
|
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.endm
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| 286 |
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#else
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| 287 |
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#if CYGHWR_HAL_ARM_EDB7XXX_VARIANT_EP7209
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| 288 |
|
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// No DRAM controller
|
| 289 |
|
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.macro INIT_MEMORY_CONFIG
|
| 290 |
|
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/* Initialize memory configuration */
|
| 291 |
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ldr r1,=MEMCFG1
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| 292 |
|
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ldr r2,=0x8200A080
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| 293 |
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str r2,[r1]
|
| 294 |
|
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ldr r1,=MEMCFG2
|
| 295 |
|
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ldr r2,=0xFEFC0000
|
| 296 |
|
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str r2,[r1]
|
| 297 |
|
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.endm
|
| 298 |
|
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#else // CYGHWR_HAL_ARM_EDB7XXX_VARIANT = EP7211, EP7212
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| 299 |
|
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.macro INIT_MEMORY_CONFIG
|
| 300 |
|
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/* Initialize memory configuration */
|
| 301 |
|
|
ldr r1,=MEMCFG1
|
| 302 |
|
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ldr r2,=0x8200A080
|
| 303 |
|
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str r2,[r1]
|
| 304 |
|
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ldr r1,=MEMCFG2
|
| 305 |
|
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ldr r2,=0xFEFC0000
|
| 306 |
|
|
str r2,[r1]
|
| 307 |
|
|
ldr r1,=DRFPR
|
| 308 |
|
|
ldr r2,=0x81 /* DRAM refresh = 64KHz */
|
| 309 |
|
|
strb r2,[r1]
|
| 310 |
|
|
.endm
|
| 311 |
|
|
#endif
|
| 312 |
|
|
#endif
|
| 313 |
|
|
|
| 314 |
|
|
#if defined(CYGSEM_HAL_STATIC_MMU_TABLES)
|
| 315 |
|
|
#define PLATFORM_SETUP1 \
|
| 316 |
|
|
INIT_MEMORY_CONFIG ;\
|
| 317 |
|
|
ldr r1,=_MMU_table-0xE0000000 ;\
|
| 318 |
|
|
MMU_INITIALIZE ;\
|
| 319 |
|
|
RELOCATE_TEXT_SEGMENT
|
| 320 |
|
|
|
| 321 |
|
|
#define PLATFORM_EXTRAS <cyg/hal/hal_platform_extras.h>
|
| 322 |
|
|
|
| 323 |
|
|
#else
|
| 324 |
|
|
// MMU tables placed in DRAM
|
| 325 |
|
|
|
| 326 |
|
|
#if (CYGHWR_HAL_ARM_EDB7XXX_DRAM_SIZE == 2)
|
| 327 |
|
|
// Note: The DRAM on this board is very irregular in that every
|
| 328 |
|
|
// other 256K piece is missing. E.g. only these [physical]
|
| 329 |
|
|
// addresses are valid:
|
| 330 |
|
|
// 0xC0000000..0xC003FFFF
|
| 331 |
|
|
// 0xC0080000..0xC00BFFFF
|
| 332 |
|
|
// 0xC0200000..0xC023FFFF Note the additional GAP!
|
| 333 |
|
|
// etc.
|
| 334 |
|
|
// 0xC0800000..0xC083FFFF Note the additional GAP!
|
| 335 |
|
|
// 0xC0880000..0xC08CFFFF
|
| 336 |
|
|
// 0xC0A00000..0xC0A3FFFF
|
| 337 |
|
|
// etc.
|
| 338 |
|
|
// The MMU mapping code takes this into consideration and creates
|
| 339 |
|
|
// a continuous logical map for the DRAM.
|
| 340 |
|
|
.macro MAP_DRAM
|
| 341 |
|
|
/* Map DRAM */
|
| 342 |
|
|
ldr r3,=DRAM_LA_START
|
| 343 |
|
|
ldr r4,=DRAM_LA_END
|
| 344 |
|
|
ldr r5,=DRAM_PA
|
| 345 |
|
|
/* 0x00000000..0x000FFFFF */
|
| 346 |
|
|
mov r6,r2 /* Set up page table descriptor */
|
| 347 |
|
|
ldr r7,=MMU_L1_TYPE_Page
|
| 348 |
|
|
orr r6,r6,r7
|
| 349 |
|
|
str r6,[r1],#4 /* Store PTE, update pointer */
|
| 350 |
|
|
10: mov r6,r5 /* Build page table entry */
|
| 351 |
|
|
ldr r7,=MMU_L2_TYPE_Small|MMU_AP_Any|MMU_Bufferable|MMU_Cacheable
|
| 352 |
|
|
orr r6,r6,r7
|
| 353 |
|
|
ldr r7,=MMU_PAGE_SIZE
|
| 354 |
|
|
str r6,[r2],#4 /* Next page */
|
| 355 |
|
|
add r3,r3,r7
|
| 356 |
|
|
add r5,r5,r7
|
| 357 |
|
|
ldr r8,=DRAM_LA_START+MMU_SECTION_SIZE
|
| 358 |
|
|
cmp r3,r8 /* Done with first 1M? */
|
| 359 |
|
|
beq 20f
|
| 360 |
|
|
ldr r7,=0x40000 /* Special check for 256K boundary */
|
| 361 |
|
|
and r7,r7,r5
|
| 362 |
|
|
cmp r7,#0
|
| 363 |
|
|
beq 10b
|
| 364 |
|
|
add r5,r5,r7 /* Skip 256K hole */
|
| 365 |
|
|
ldr r7,=0x100000
|
| 366 |
|
|
and r7,r5,r7
|
| 367 |
|
|
beq 10b
|
| 368 |
|
|
add r5,r5,r7 /* Nothing at 0xC0100000 */
|
| 369 |
|
|
ldr r7,=0x400000 /* Also nothing at 0xC0400000 */
|
| 370 |
|
|
and r7,r5,r7
|
| 371 |
|
|
beq 10b
|
| 372 |
|
|
add r5,r5,r7
|
| 373 |
|
|
b 10b
|
| 374 |
|
|
20:
|
| 375 |
|
|
/* 0x00100000..0x001FFFFF */
|
| 376 |
|
|
mov r6,r2 /* Set up page table descriptor */
|
| 377 |
|
|
ldr r7,=MMU_L1_TYPE_Page
|
| 378 |
|
|
orr r6,r6,r7
|
| 379 |
|
|
str r6,[r1],#4 /* Store PTE, update pointer */
|
| 380 |
|
|
10: mov r6,r5 /* Build page table entry */
|
| 381 |
|
|
ldr r7,=MMU_L2_TYPE_Small|MMU_AP_Any|MMU_Bufferable|MMU_Cacheable
|
| 382 |
|
|
orr r6,r6,r7
|
| 383 |
|
|
ldr r7,=MMU_PAGE_SIZE
|
| 384 |
|
|
str r6,[r2],#4 /* Next page */
|
| 385 |
|
|
add r3,r3,r7
|
| 386 |
|
|
cmp r3,r4 /* Done with first DRAM? */
|
| 387 |
|
|
beq 20f
|
| 388 |
|
|
add r5,r5,r7
|
| 389 |
|
|
ldr r7,=0x40000 /* Special check for 256K boundary */
|
| 390 |
|
|
and r7,r7,r5
|
| 391 |
|
|
cmp r7,#0
|
| 392 |
|
|
beq 10b
|
| 393 |
|
|
add r5,r5,r7 /* Skip 256K hole */
|
| 394 |
|
|
ldr r7,=0x100000
|
| 395 |
|
|
and r7,r5,r7
|
| 396 |
|
|
beq 10b
|
| 397 |
|
|
add r5,r5,r7 /* Nothing at 0xC0300000 */
|
| 398 |
|
|
ldr r7,=0x400000 /* Also nothing at 0xC0400000 */
|
| 399 |
|
|
and r7,r5,r7
|
| 400 |
|
|
beq 10b
|
| 401 |
|
|
add r5,r5,r7
|
| 402 |
|
|
b 10b
|
| 403 |
|
|
20:
|
| 404 |
|
|
|
| 405 |
|
|
#elif (CYGHWR_HAL_ARM_EDB7XXX_DRAM_SIZE == 16)
|
| 406 |
|
|
// The 16M EDB72xx boards are arranged as:
|
| 407 |
|
|
// 0xC0000000..0xC07FFFFF
|
| 408 |
|
|
// 0xC1000000..0xC17FFFFF
|
| 409 |
|
|
// The 16M EDB7312 board is arranged as:
|
| 410 |
|
|
// 0xC0000000..0xC0FFFFFF
|
| 411 |
|
|
.macro MAP_DRAM
|
| 412 |
|
|
/* Map DRAM */
|
| 413 |
|
|
ldr r3,=DRAM_LA_START
|
| 414 |
|
|
ldr r4,=DRAM_LA_END
|
| 415 |
|
|
ldr r5,=DRAM_PA
|
| 416 |
|
|
/* 0xXXX00000..0xXXXFFFFF */
|
| 417 |
|
|
10: mov r6,r2 /* Set up page table descriptor */
|
| 418 |
|
|
ldr r7,=MMU_L1_TYPE_Page
|
| 419 |
|
|
orr r6,r6,r7
|
| 420 |
|
|
str r6,[r1],#4 /* Store PTE, update pointer */
|
| 421 |
|
|
ldr r8,=MMU_SECTION_SIZE/MMU_PAGE_SIZE
|
| 422 |
|
|
#if !defined(__EDB7312)
|
| 423 |
|
|
// EDB7312 has contiguous SDRAM
|
| 424 |
|
|
ldr r9,=DRAM_PA_START+0x00800000 /* Skip at 8M boundary */
|
| 425 |
|
|
12: cmp r5,r9
|
| 426 |
|
|
bne 15f
|
| 427 |
|
|
ldr r5,=DRAM_PA_START+0x01000000 /* Next chunk of DRAM */
|
| 428 |
|
|
#else
|
| 429 |
|
|
12:
|
| 430 |
|
|
#endif
|
| 431 |
|
|
15: mov r6,r5 /* Build page table entry */
|
| 432 |
|
|
ldr r7,=MMU_L2_TYPE_Small|MMU_AP_Any|MMU_Bufferable|MMU_Cacheable
|
| 433 |
|
|
orr r6,r6,r7
|
| 434 |
|
|
ldr r7,=MMU_PAGE_SIZE
|
| 435 |
|
|
str r6,[r2],#4 /* Next page */
|
| 436 |
|
|
add r3,r3,r7
|
| 437 |
|
|
add r5,r5,r7
|
| 438 |
|
|
cmp r3,r4 /* End of DRAM? */
|
| 439 |
|
|
beq 20f
|
| 440 |
|
|
sub r8,r8,#1 /* End of 1M section? */
|
| 441 |
|
|
cmp r8,#0
|
| 442 |
|
|
bne 12b /* Next page */
|
| 443 |
|
|
b 10b /* Next section */
|
| 444 |
|
|
20:
|
| 445 |
|
|
.endm
|
| 446 |
|
|
#else
|
| 447 |
|
|
#error Invalid DRAM size select
|
| 448 |
|
|
#endif
|
| 449 |
|
|
|
| 450 |
|
|
.macro MAP_L1_SEGMENT start end phys prot
|
| 451 |
|
|
ldr r3,=0x3FF /* Page tables need 2K boundary */
|
| 452 |
|
|
add r2,r2,r3
|
| 453 |
|
|
ldr r3,=~0x3FF
|
| 454 |
|
|
and r2,r2,r3
|
| 455 |
|
|
ldr r3,=\start
|
| 456 |
|
|
ldr r4,=\end
|
| 457 |
|
|
ldr r5,=\phys
|
| 458 |
|
|
ldr r6,=\prot
|
| 459 |
|
|
ldr r7,=MMU_SECTION_SIZE
|
| 460 |
|
|
10: orr r0,r5,r6
|
| 461 |
|
|
str r0,[r1],#4
|
| 462 |
|
|
add r5,r5,r7
|
| 463 |
|
|
add r3,r3,r7
|
| 464 |
|
|
cmp r3,r4
|
| 465 |
|
|
bne 10b
|
| 466 |
|
|
.endm
|
| 467 |
|
|
|
| 468 |
|
|
.macro PLATFORM_SETUP1
|
| 469 |
|
|
INIT_MEMORY_CONFIG
|
| 470 |
|
|
#ifdef CYG_HAL_STARTUP_RAM
|
| 471 |
|
|
RELOCATE_RAM_IMAGE
|
| 472 |
|
|
#endif
|
| 473 |
|
|
/* Initialize MMU to create new memory map */
|
| 474 |
|
|
ldr r1,=MMU_BASE
|
| 475 |
|
|
ldr r2,=PTE_BASE
|
| 476 |
|
|
MAP_DRAM
|
| 477 |
|
|
/* Nothing until PCMCIA0 */
|
| 478 |
|
|
MAP_L1_SEGMENT (DRAM_LA_END+0x000FFFFF)&0xFFF00000 EXPANSION2_LA_START 0 MMU_L1_TYPE_Fault
|
| 479 |
|
|
/* EXPANSION2, EXPANSION3, PCMCIA0, PCMCIA1 */
|
| 480 |
|
|
MAP_L1_SEGMENT EXPANSION2_LA_START SRAM_LA_START EXPANSION2_PA MMU_L1_TYPE_Section|MMU_AP_Any
|
| 481 |
|
|
/* SRAM */
|
| 482 |
|
|
ldr r3,=SRAM_LA_START
|
| 483 |
|
|
ldr r4,=MMU_L1_TYPE_Page|MMU_DOMAIN(0)
|
| 484 |
|
|
orr r4,r4,r2
|
| 485 |
|
|
str r4,[r1],#4
|
| 486 |
|
|
ldr r7,=MMU_PAGE_SIZE
|
| 487 |
|
|
ldr r5,=SRAM_LA_END
|
| 488 |
|
|
05: ldr r4,=MMU_L2_TYPE_Small|MMU_AP_Any|MMU_Bufferable|MMU_Cacheable
|
| 489 |
|
|
orr r4,r3,r4
|
| 490 |
|
|
str r4,[r2],#4
|
| 491 |
|
|
add r3,r3,r7
|
| 492 |
|
|
cmp r3,r5
|
| 493 |
|
|
bne 05b
|
| 494 |
|
|
ldr r4,=SRAM_LA_START+MMU_SECTION_SIZE
|
| 495 |
|
|
ldr r5,=MMU_L2_TYPE_Fault
|
| 496 |
|
|
10: str r5,[r2],#4
|
| 497 |
|
|
add r3,r3,r7
|
| 498 |
|
|
cmp r3,r4
|
| 499 |
|
|
bne 10b
|
| 500 |
|
|
ldr r4,=IO_LA_START
|
| 501 |
|
|
ldr r5,=MMU_L1_TYPE_Fault
|
| 502 |
|
|
ldr r7,=MMU_SECTION_SIZE
|
| 503 |
|
|
20: str r5,[r1],#4
|
| 504 |
|
|
add r3,r3,r7
|
| 505 |
|
|
cmp r3,r4
|
| 506 |
|
|
bne 20b
|
| 507 |
|
|
/* I/O */
|
| 508 |
|
|
ldr r3,=0x3FF /* Page tables need 2K boundary */
|
| 509 |
|
|
add r2,r2,r3
|
| 510 |
|
|
ldr r3,=~0x3FF
|
| 511 |
|
|
and r2,r2,r3
|
| 512 |
|
|
ldr r4,=MMU_L1_TYPE_Page|MMU_DOMAIN(0)
|
| 513 |
|
|
orr r4,r4,r2
|
| 514 |
|
|
str r4,[r1],#4
|
| 515 |
|
|
ldr r3,=IO_LA_START
|
| 516 |
|
|
ldr r4,=IO_LA_END
|
| 517 |
|
|
ldr r7,=MMU_PAGE_SIZE
|
| 518 |
|
|
ldr r5,=IO_PA|MMU_L2_TYPE_Small|MMU_AP_All
|
| 519 |
|
|
10: str r5,[r2],#4
|
| 520 |
|
|
add r5,r5,r7
|
| 521 |
|
|
add r3,r3,r7
|
| 522 |
|
|
cmp r3,r4
|
| 523 |
|
|
bne 10b
|
| 524 |
|
|
ldr r4,=IO_LA_START+MMU_SECTION_SIZE
|
| 525 |
|
|
ldr r5,=MMU_L2_TYPE_Fault
|
| 526 |
|
|
ldr r7,=MMU_PAGE_SIZE
|
| 527 |
|
|
10: str r5,[r2],#4
|
| 528 |
|
|
add r3,r3,r7
|
| 529 |
|
|
cmp r3,r4
|
| 530 |
|
|
bne 10b
|
| 531 |
|
|
ldr r4,=LCD_LA_START
|
| 532 |
|
|
ldr r5,=MMU_L1_TYPE_Fault
|
| 533 |
|
|
ldr r7,=MMU_SECTION_SIZE
|
| 534 |
|
|
20: str r5,[r1],#4
|
| 535 |
|
|
add r3,r3,r7
|
| 536 |
|
|
cmp r3,r4
|
| 537 |
|
|
bne 20b
|
| 538 |
|
|
/* LCD Buffer & Unmapped DRAM (holes and all) */
|
| 539 |
|
|
MAP_L1_SEGMENT LCD_LA_START ROM0_LA_START LCD_PA MMU_L1_TYPE_Section|MMU_AP_Any|MMU_Bufferable|MMU_Cacheable
|
| 540 |
|
|
/* ROM0 */
|
| 541 |
|
|
MAP_L1_SEGMENT ROM0_LA_START ROM0_LA_END ROM0_PA MMU_L1_TYPE_Section|MMU_AP_Any
|
| 542 |
|
|
/* ROM1 */
|
| 543 |
|
|
MAP_L1_SEGMENT ROM1_LA_START ROM1_LA_END ROM1_PA MMU_L1_TYPE_Section|MMU_AP_Any
|
| 544 |
|
|
/* Now initialize the MMU to use this new page table */
|
| 545 |
|
|
ldr r1,=MMU_BASE
|
| 546 |
|
|
MMU_INITIALIZE
|
| 547 |
|
|
#ifdef CYG_HAL_STARTUP_ROMRAM
|
| 548 |
|
|
RELOCATE_TEXT_SEGMENT
|
| 549 |
|
|
#endif // CYG_HAL_STARTUP_ROM
|
| 550 |
|
|
.endm
|
| 551 |
|
|
#endif // CYGSEM_HAL_STATIC_MMU_TABLES
|
| 552 |
|
|
|
| 553 |
|
|
#else // CYGSEM_HAL_INSTALL_MMU_TABLES
|
| 554 |
|
|
|
| 555 |
|
|
#define PLATFORM_SETUP1
|
| 556 |
|
|
#endif
|
| 557 |
|
|
#endif //_CYGHWR_LAYOUT_ONLY
|
| 558 |
|
|
|
| 559 |
|
|
/*---------------------------------------------------------------------------*/
|
| 560 |
|
|
/* end of hal_platform_setup.h */
|
| 561 |
|
|
#endif /* CYGONCE_HAL_PLATFORM_SETUP_H */
|
