OpenCores
URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [rtos/] [ecos-2.0/] [packages/] [hal/] [arm/] [edb7xxx/] [v2_0/] [include/] [pkgconf/] [mlt_arm_edb7211_ram.h] - Blame information for rev 390

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 27 unneback
// eCos memory layout - Fri Oct 20 05:38:50 2000
2
 
3
// This is a generated file - do not edit
4
 
5
#ifndef __ASSEMBLER__
6
#include <cyg/infra/cyg_type.h>
7
#include <stddef.h>
8
 
9
#endif
10
#define CYGMEM_REGION_ram (0)
11
#define CYGMEM_REGION_ram_SIZE (0xfd7000)
12
#define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
13
#ifndef __ASSEMBLER__
14
extern char CYG_LABEL_NAME (__heap1) [];
15
#endif
16
#define CYGMEM_SECTION_heap1 (CYG_LABEL_NAME (__heap1))
17
#define CYGMEM_SECTION_heap1_SIZE (0xfd7000 - (size_t) CYG_LABEL_NAME (__heap1))

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.