OpenCores
URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [rtos/] [ecos-2.0/] [packages/] [hal/] [arm/] [edb7xxx/] [v2_0/] [include/] [pkgconf/] [mlt_arm_edb7312_romram.mlt] - Blame information for rev 174

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 27 unneback
version 0
2
region ram 0 fd0000 0 !
3
region sram 60000000 9c00 0 !
4
section fixed_vectors 0 1 0 1 1 0 1 0 20 20 !
5
section rom_vectors 0 1 0 1 1 1 1 1 1000 1000 text text !
6
section text 0 4 0 1 0 1 0 1 fini fini !
7
section fini 0 4 0 1 0 1 0 1 rodata rodata !
8
section rodata 0 4 0 1 0 1 0 1 rodata1 rodata1 !
9
section rodata1 0 4 0 1 0 1 0 1 fixup fixup !
10
section fixup 0 4 0 1 0 1 0 1 gcc_except_table gcc_except_table !
11
section gcc_except_table 0 4 0 1 0 1 0 1 data data !
12
section data 0 4 0 1 0 1 0 1 bss bss !
13
section bss 0 4 0 1 0 1 0 1 heap1 heap1 !
14
section heap1 0 8 0 0 0 0 0 0 !
15
section sram 0 1 0 1 1 0 1 0 60000000 60000000 !

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.