OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [rtos/] [ecos-2.0/] [packages/] [hal/] [arm/] [integrator/] [v2_0/] [include/] [hal_cache.h] - Blame information for rev 587

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 27 unneback
#ifndef CYGONCE_HAL_CACHE_H
2
#define CYGONCE_HAL_CACHE_H
3
 
4
//=============================================================================
5
//
6
//      hal_cache.h
7
//
8
//      HAL cache control API
9
//
10
//=============================================================================
11
//####ECOSGPLCOPYRIGHTBEGIN####
12
// -------------------------------------------
13
// This file is part of eCos, the Embedded Configurable Operating System.
14
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
15
//
16
// eCos is free software; you can redistribute it and/or modify it under
17
// the terms of the GNU General Public License as published by the Free
18
// Software Foundation; either version 2 or (at your option) any later version.
19
//
20
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
21
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
22
// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
23
// for more details.
24
//
25
// You should have received a copy of the GNU General Public License along
26
// with eCos; if not, write to the Free Software Foundation, Inc.,
27
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
28
//
29
// As a special exception, if other files instantiate templates or use macros
30
// or inline functions from this file, or you compile this file and link it
31
// with other works to produce a work based on this file, this file does not
32
// by itself cause the resulting work to be covered by the GNU General Public
33
// License. However the source code for this file must still be made available
34
// in accordance with section (3) of the GNU General Public License.
35
//
36
// This exception does not invalidate any other reasons why a work based on
37
// this file might be covered by the GNU General Public License.
38
//
39
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
40
// at http://sources.redhat.com/ecos/ecos-license/
41
// -------------------------------------------
42
//####ECOSGPLCOPYRIGHTEND####
43
//=============================================================================
44
//#####DESCRIPTIONBEGIN####
45
//
46
// Author(s):    David A Rusling
47
// Contributors: Philippe Robin
48
// Date:         November 7, 2000
49
// Purpose:      Cache control API
50
// Description:  The macros defined here provide the HAL APIs for handling
51
//               cache control operations.
52
// Usage:
53
//               #include <cyg/hal/hal_cache.h>
54
//               ...
55
//              
56
//
57
//####DESCRIPTIONEND####
58
//
59
//=============================================================================
60
 
61
#include <cyg/infra/cyg_type.h>
62
 
63
//-----------------------------------------------------------------------------
64
// Cache dimensions
65
 
66
// Data cache
67
#define HAL_DCACHE_SIZE                 0    // Size of data cache in bytes
68
#define HAL_DCACHE_LINE_SIZE            0    // Size of a data cache line
69
#define HAL_DCACHE_WAYS                 0    // Associativity of the cache
70
 
71
// Instruction cache
72
#define HAL_ICACHE_SIZE                 0    // Size of cache in bytes
73
#define HAL_ICACHE_LINE_SIZE            0    // Size of a cache line
74
#define HAL_ICACHE_WAYS                 0    // Associativity of the cache
75
 
76
#define HAL_DCACHE_SETS (HAL_DCACHE_SIZE/(HAL_DCACHE_LINE_SIZE*HAL_DCACHE_WAYS))
77
#define HAL_ICACHE_SETS (HAL_ICACHE_SIZE/(HAL_ICACHE_LINE_SIZE*HAL_ICACHE_WAYS))
78
 
79
//-----------------------------------------------------------------------------
80
// Global control of data cache
81
 
82
// Enable the data cache
83
#define HAL_DCACHE_ENABLE()
84
 
85
// Disable the data cache
86
#define HAL_DCACHE_DISABLE()
87
 
88
// Invalidate the entire cache
89
#define HAL_DCACHE_INVALIDATE_ALL()
90
 
91
// Synchronize the contents of the cache with memory.
92
#define HAL_DCACHE_SYNC()
93
 
94
// Query the state of the data cache
95
#define HAL_DCACHE_IS_ENABLED(_state_)  0
96
 
97
// Purge contents of data cache
98
#define HAL_DCACHE_PURGE_ALL()
99
 
100
// Set the data cache refill burst size
101
//#define HAL_DCACHE_BURST_SIZE(_size_)
102
 
103
// Set the data cache write mode
104
//#define HAL_DCACHE_WRITE_MODE( _mode_ )
105
 
106
//#define HAL_DCACHE_WRITETHRU_MODE       0
107
//#define HAL_DCACHE_WRITEBACK_MODE       1
108
 
109
// Load the contents of the given address range into the data cache
110
// and then lock the cache so that it stays there.
111
//#define HAL_DCACHE_LOCK(_base_, _size_)
112
 
113
// Undo a previous lock operation
114
//#define HAL_DCACHE_UNLOCK(_base_, _size_)
115
 
116
// Unlock entire cache
117
//#define HAL_DCACHE_UNLOCK_ALL()
118
 
119
//-----------------------------------------------------------------------------
120
// Data cache line control
121
 
122
// Allocate cache lines for the given address range without reading its
123
// contents from memory.
124
//#define HAL_DCACHE_ALLOCATE( _base_ , _size_ )
125
 
126
// Write dirty cache lines to memory and invalidate the cache entries
127
// for the given address range.
128
//#define HAL_DCACHE_FLUSH( _base_ , _size_ )
129
 
130
// Invalidate cache lines in the given range without writing to memory.
131
//#define HAL_DCACHE_INVALIDATE( _base_ , _size_ )
132
 
133
// Write dirty cache lines to memory for the given address range.
134
//#define HAL_DCACHE_STORE( _base_ , _size_ )
135
 
136
// Preread the given range into the cache with the intention of reading
137
// from it later.
138
//#define HAL_DCACHE_READ_HINT( _base_ , _size_ )
139
 
140
// Preread the given range into the cache with the intention of writing
141
// to it later.
142
//#define HAL_DCACHE_WRITE_HINT( _base_ , _size_ )
143
 
144
// Allocate and zero the cache lines associated with the given range.
145
//#define HAL_DCACHE_ZERO( _base_ , _size_ )
146
 
147
//-----------------------------------------------------------------------------
148
// Global control of Instruction cache
149
 
150
// Enable the instruction cache
151
#define HAL_ICACHE_ENABLE()
152
 
153
// Disable the instruction cache
154
#define HAL_ICACHE_DISABLE()
155
 
156
// Invalidate the entire cache
157
#define HAL_ICACHE_INVALIDATE_ALL()
158
 
159
// Synchronize the contents of the cache with memory.
160
#define HAL_ICACHE_SYNC()
161
 
162
// Set the instruction cache refill burst size
163
//#define HAL_ICACHE_BURST_SIZE(_size_)
164
 
165
// Load the contents of the given address range into the instruction cache
166
// and then lock the cache so that it stays there.
167
//#define HAL_ICACHE_LOCK(_base_, _size_)
168
 
169
// Undo a previous lock operation
170
//#define HAL_ICACHE_UNLOCK(_base_, _size_)
171
 
172
// Unlock entire cache
173
//#define HAL_ICACHE_UNLOCK_ALL()
174
 
175
//-----------------------------------------------------------------------------
176
// Instruction cache line control
177
 
178
// Invalidate cache lines in the given range without writing to memory.
179
//#define HAL_ICACHE_INVALIDATE( _base_ , _size_ )
180
 
181
//-----------------------------------------------------------------------------
182
#endif // ifndef CYGONCE_HAL_CACHE_H
183
// End of hal_cache.h

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.