OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [rtos/] [ecos-2.0/] [packages/] [hal/] [arm/] [integrator/] [v2_0/] [include/] [pkgconf/] [mlt_arm_integrator_ram.mlt] - Blame information for rev 174

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 27 unneback 
version 0
2 
region ram 0 01000000 0 !
3 
section reserved 8000 1 0 0 1 1 1 1 0 0 rom_vectors rom_vectors !
4 
section rom_vectors 0 4 0 1 0 1 0 1 text text !
5 
section text 0 4 0 1 0 1 0 1 fini fini !
6 
section fini 0 4 0 1 0 1 0 1 rodata rodata !
7 
section rodata 0 4 0 1 0 1 0 1 rodata1 rodata1 !
8 
section rodata1 0 4 0 1 0 1 0 1 fixup fixup !
9 
section fixup 0 4 0 1 0 1 0 1 gcc_except_table gcc_except_table !
10 
section gcc_except_table 0 4 0 1 0 1 0 1 data data !
11 
section data 0 4 0 1 0 1 0 1 bss bss !
12 
section bss 0 4 0 1 0 0 0 0 !

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.