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#ifndef CYGONCE_PLF_IO_H
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#define CYGONCE_PLF_IO_H
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//=============================================================================
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//
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// plf_io.h
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//
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// Platform specific IO support
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//
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//=============================================================================
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//####ECOSGPLCOPYRIGHTBEGIN####
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// -------------------------------------------
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// This file is part of eCos, the Embedded Configurable Operating System.
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// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
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//
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// eCos is free software; you can redistribute it and/or modify it under
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// the terms of the GNU General Public License as published by the Free
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// Software Foundation; either version 2 or (at your option) any later version.
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//
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// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// for more details.
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//
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// You should have received a copy of the GNU General Public License along
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// with eCos; if not, write to the Free Software Foundation, Inc.,
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// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
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//
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// As a special exception, if other files instantiate templates or use macros
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// or inline functions from this file, or you compile this file and link it
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// with other works to produce a work based on this file, this file does not
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// by itself cause the resulting work to be covered by the GNU General Public
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// License. However the source code for this file must still be made available
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// in accordance with section (3) of the GNU General Public License.
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//
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// This exception does not invalidate any other reasons why a work based on
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// this file might be covered by the GNU General Public License.
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//
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// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
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// at http://sources.redhat.com/ecos/ecos-license/
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// -------------------------------------------
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//####ECOSGPLCOPYRIGHTEND####
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//=============================================================================
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//#####DESCRIPTIONBEGIN####
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//
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// Author(s): Philippe Robin
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// Contributors: David A Rusling
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// Date: November 7, 2000
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// Purpose: Integrator PCI IO support macros
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// Description:
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// Usage: #include <cyg/hal/plf_io.h>
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//
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//####DESCRIPTIONEND####
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//
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//=============================================================================
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#include <pkgconf/hal_arm_integrator.h>
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#include <cyg/hal/hal_integrator.h>
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#include <cyg/hal/hal_platform_ints.h> // Interrupt vectors
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__externC void cyg_plf_pci_init(void);
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// Initialization of the PCI bus.
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#define HAL_PCI_INIT() cyg_plf_pci_init()
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// V3 access routines
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#define _V3Write16(o,v) (*(volatile cyg_uint16 *)(PCI_V3_BASE + (cyg_uint32)(o)) \
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= (cyg_uint16)(v))
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#define _V3Read16(o) (*(volatile cyg_uint16 *)(PCI_V3_BASE + (cyg_uint32)(o)))
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#define _V3Write32(o,v) (*(volatile cyg_uint32 *)(PCI_V3_BASE + (cyg_uint32)(o)) \
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= (cyg_uint32)(v))
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#define _V3Read32(o) (*(volatile cyg_uint32 *)(PCI_V3_BASE + (cyg_uint32)(o)))
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// _V3OpenConfigWindow - open V3 configuration window
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#define _V3OpenConfigWindow() \
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{ \
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/* Set up base0 to see all 512Mbytes of memory space (not */ \
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/* prefetchable), this frees up base1 for re-use by configuration*/ \
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/* memory */ \
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\
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_V3Write32 (V3_LB_BASE0, ((INTEGRATOR_PCI_BASE & 0xFFF00000) | \
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0x90 | V3_LB_BASE_M_ENABLE)); \
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/* Set up base1 to point into configuration space, note that MAP1 */ \
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/* register is set up by pciMakeConfigAddress(). */ \
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\
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_V3Write32 (V3_LB_BASE1, ((CPU_PCI_CNFG_ADRS & 0xFFF00000) | \
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0x40 | V3_LB_BASE_M_ENABLE)); \
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}
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// _V3CloseConfigWindow - close V3 configuration window
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#define _V3CloseConfigWindow() \
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{ \
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/* Reassign base1 for use by prefetchable PCI memory */ \
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_V3Write32 (V3_LB_BASE1, (((INTEGRATOR_PCI_BASE + SZ_256M) & 0xFFF00000) \
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| 0x84 | V3_LB_BASE_M_ENABLE)); \
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_V3Write16 (V3_LB_MAP1, \
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(((INTEGRATOR_PCI_BASE + SZ_256M) & 0xFFF00000) >> 16) | 0x0006); \
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\
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/* And shrink base0 back to a 256M window (NOTE: MAP0 already correct) */ \
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\
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_V3Write32 (V3_LB_BASE0, ((INTEGRATOR_PCI_BASE & 0xFFF00000) | \
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0x80 | V3_LB_BASE_M_ENABLE)); \
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}
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// Compute address necessary to access PCI config space for the given
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// bus and device.
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#define HAL_PCI_CONFIG_ADDRESS( __bus, __devfn, __offset ) \
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({ \
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cyg_uint32 __address, __devicebit; \
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cyg_uint16 __mapaddress; \
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cyg_uint32 __dev = CYG_PCI_DEV_GET_DEV(__devfn); /* FIXME to check!! (slot?) */ \
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\
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if (__bus == 0) { \
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/* local bus segment so need a type 0 config cycle */ \
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/* build the PCI configuration "address" with one-hot in A31-A11 */ \
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__address = PCI_CONFIG_BASE; \
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__address |= ((__devfn & 0x07) << 8); \
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__address |= __offset & 0xFF; \
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__mapaddress = 0x000A; /* 101=>config cycle, 0=>A1=A0=0 */ \
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__devicebit = (1 << (__dev + 11)); \
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\
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if ((__devicebit & 0xFF000000) != 0) { \
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/* high order bits are handled by the MAP register */ \
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__mapaddress |= (__devicebit >> 16); \
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} else { \
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/* low order bits handled directly in the address */ \
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__address |= __devicebit; \
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} \
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} else { /* bus !=0 */ \
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/* not the local bus segment so need a type 1 config cycle */ \
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/* A31-A24 are don't care (so clear to 0) */ \
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__mapaddress = 0x000B; /* 101=>config cycle, 1=>A1&A0 from PCI_CFG */ \
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__address = PCI_CONFIG_BASE; \
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__address |= ((__bus & 0xFF) << 16); /* bits 23..16 = bus number */ \
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__address |= ((__dev & 0x1F) << 11); /* bits 15..11 = device number */ \
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__address |= ((__devfn & 0x07) << 8); /* bits 10..8 = function number*/ \
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__address |= __offset & 0xFF; /* bits 7..0 = register number*/ \
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} \
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_V3Write16(V3_LB_MAP1, __mapaddress); \
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\
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__address; \
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})
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// Read a value from the PCI configuration space of the appropriate
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// size at an address composed from the bus, devfn and offset.
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#define HAL_PCI_CFG_READ_UINT8( __bus, __devfn, __offset, __val ) \
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{ \
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_V3OpenConfigWindow(); \
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__val = *(volatile cyg_uint8 *)HAL_PCI_CONFIG_ADDRESS(__bus, __devfn, __offset); \
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_V3CloseConfigWindow(); \
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}
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#define HAL_PCI_CFG_READ_UINT16( __bus, __devfn, __offset, __val ) \
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{ \
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_V3OpenConfigWindow(); \
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__val = *(volatile cyg_uint16 *)HAL_PCI_CONFIG_ADDRESS(__bus, __devfn, __offset); \
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_V3CloseConfigWindow(); \
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}
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#define HAL_PCI_CFG_READ_UINT32( __bus, __devfn, __offset, __val ) \
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{ \
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_V3OpenConfigWindow(); \
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__val = *(volatile cyg_uint16 *)HAL_PCI_CONFIG_ADDRESS(__bus, __devfn, __offset); \
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__val |= (*(volatile cyg_uint16 *)HAL_PCI_CONFIG_ADDRESS(__bus, __devfn, (__offset+2)))<<16; \
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_V3CloseConfigWindow(); \
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}
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// Write a value to the PCI configuration space of the appropriate
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// size at an address composed from the bus, devfn and offset.
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#define HAL_PCI_CFG_WRITE_UINT8( __bus, __devfn, __offset, __val ) \
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{ \
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_V3OpenConfigWindow(); \
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*(volatile cyg_uint8 *)HAL_PCI_CONFIG_ADDRESS(__bus, __devfn, __offset) = __val; \
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_V3CloseConfigWindow(); \
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}
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#define HAL_PCI_CFG_WRITE_UINT16( __bus, __devfn, __offset, __val ) \
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{ \
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_V3OpenConfigWindow(); \
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*(volatile cyg_uint16 *)HAL_PCI_CONFIG_ADDRESS(__bus, __devfn, __offset) = __val; \
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_V3CloseConfigWindow(); \
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}
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#define HAL_PCI_CFG_WRITE_UINT32( __bus, __devfn, __offset, __val ) \
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{ \
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_V3OpenConfigWindow(); \
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*(volatile cyg_uint16 *)HAL_PCI_CONFIG_ADDRESS((__bus), (__devfn), (__offset)) = ((__val) & 0xFFFF); \
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*(volatile cyg_uint16 *)HAL_PCI_CONFIG_ADDRESS((__bus), (__devfn), ((__offset)+2)) = (((__val)>>16) & 0xFFFF); \
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_V3CloseConfigWindow(); \
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}
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//-----------------------------------------------------------------------------
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// Resources
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// Map PCI device resources starting from these addresses in PCI space.
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#define HAL_PCI_ALLOC_BASE_MEMORY 0
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#define HAL_PCI_ALLOC_BASE_IO 0x4000
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// This is where the PCI spaces are mapped in the CPU's address space.
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#define HAL_PCI_PHYSICAL_MEMORY_BASE (PCI_MEM_BASE)
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#define HAL_PCI_PHYSICAL_IO_BASE (PCI_IO_BASE)
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// Translate the PCI interrupt requested by the device (INTA#, INTB#,
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// INTC# or INTD#) to the associated CPU interrupt (i.e., HAL vector).
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#define INTA CYGNUM_HAL_INTERRUPT_PCIINT0
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#define INTB CYGNUM_HAL_INTERRUPT_PCIINT1
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#define INTC CYGNUM_HAL_INTERRUPT_PCIINT2
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#define INTD CYGNUM_HAL_INTERRUPT_PCIINT3
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#define HAL_PCI_TRANSLATE_INTERRUPT( __bus, __devfn, __vec, __valid) \
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CYG_MACRO_START \
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cyg_uint8 __req; \
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cyg_uint32 __dev; \
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/* DANGER! For now this is the SDM interrupt table... */ \
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static const cyg_uint8 irq_tab[12][4] = { \
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/* INTA INTB INTC INTD */ \
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{INTA, INTB, INTC, INTD}, /* idsel 20, slot 9 */ \
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{INTB, INTC, INTD, INTA}, /* idsel 21, slot 10 */ \
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{INTC, INTD, INTA, INTB}, /* idsel 22, slot 11 */ \
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{INTD, INTA, INTB, INTC}, /* idsel 23, slot 12 */ \
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{INTA, INTB, INTC, INTD}, /* idsel 24, slot 13 */ \
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{INTB, INTC, INTD, INTA}, /* idsel 25, slot 14 */ \
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{INTC, INTD, INTA, INTB}, /* idsel 26, slot 15 */ \
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{INTD, INTA, INTB, INTC}, /* idsel 27, slot 16 */ \
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{INTA, INTB, INTC, INTD}, /* idsel 28, slot 17 */ \
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{INTB, INTC, INTD, INTA}, /* idsel 29, slot 18 */ \
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{INTC, INTD, INTA, INTB}, /* idsel 30, slot 19 */ \
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{INTD, INTA, INTB, INTC} /* idsel 31, slot 20 */ \
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}; \
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HAL_PCI_CFG_READ_UINT8(__bus, __devfn, CYG_PCI_CFG_INT_PIN, __req); \
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__dev = CYG_PCI_DEV_GET_DEV(__devfn); /* FIXME to check!! (slot?)*/ \
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\
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/* if PIN = 0, default to A */ \
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if (__req == 0) \
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__req = 1; \
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\
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__vec = irq_tab[__dev - 9][__req - 1]; \
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__valid = true; \
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CYG_MACRO_END
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//-----------------------------------------------------------------------------
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#define CYGARC_PHYSICAL_ADDRESS(x) (x)
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//-----------------------------------------------------------------------------
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// end of plf_io.h
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#endif // CYGONCE_PLF_IO_H
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