OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [rtos/] [ecos-2.0/] [packages/] [hal/] [arm/] [pid/] [v2_0/] [misc/] [redboot_RAM.ecm] - Blame information for rev 27

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 27 unneback
cdl_savefile_version 1;
2
cdl_savefile_command cdl_savefile_version {};
3
cdl_savefile_command cdl_savefile_command {};
4
cdl_savefile_command cdl_configuration { description hardware template package };
5
cdl_savefile_command cdl_package { value_source user_value wizard_value inferred_value };
6
cdl_savefile_command cdl_component { value_source user_value wizard_value inferred_value };
7
cdl_savefile_command cdl_option { value_source user_value wizard_value inferred_value };
8
cdl_savefile_command cdl_interface { value_source user_value wizard_value inferred_value };
9
 
10
cdl_configuration eCos {
11
    description "" ;
12
    hardware    pid ;
13
    template    redboot ;
14
    package -hardware CYGPKG_HAL_ARM v2_0 ;
15
    package -hardware CYGPKG_HAL_ARM_PID v2_0 ;
16
    package -hardware CYGPKG_IO_SERIAL_GENERIC_16X5X v2_0 ;
17
    package -hardware CYGPKG_IO_SERIAL_ARM_PID v2_0 ;
18
    package -hardware CYGPKG_DEVS_FLASH_ARM_PID v2_0 ;
19
    package -hardware CYGPKG_DEVS_FLASH_ATMEL_AT29CXXXX v2_0 ;
20
    package -template CYGPKG_HAL v2_0 ;
21
    package -template CYGPKG_INFRA v2_0 ;
22
    package -template CYGPKG_REDBOOT v2_0 ;
23
    package CYGPKG_IO_FLASH v2_0 ;
24
};
25
 
26
cdl_option CYGBLD_BUILD_GDB_STUBS {
27
    user_value 0
28
};
29
 
30
cdl_option CYGDBG_HAL_COMMON_INTERRUPTS_SAVE_MINIMUM_CONTEXT {
31
    user_value 0
32
};
33
 
34
cdl_option CYGDBG_HAL_COMMON_CONTEXT_SAVE_MINIMUM {
35
    inferred_value 0
36
};
37
 
38
cdl_option CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS {
39
    inferred_value 1
40
};
41
 
42
cdl_option CYGSEM_HAL_USE_ROM_MONITOR {
43
    inferred_value 0 0
44
};
45
 
46
cdl_component CYGBLD_BUILD_REDBOOT {
47
    user_value 1
48
};
49
 
50
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.