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[/] [openrisc/] [trunk/] [rtos/] [ecos-2.0/] [packages/] [hal/] [arm/] [pid/] [v2_0/] [src/] [hal_diag.c] - Blame information for rev 174

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/*=============================================================================
2
//
3
//      hal_diag.c
4
//
5
//      HAL diagnostic output code
6
//
7
//=============================================================================
8
//####ECOSGPLCOPYRIGHTBEGIN####
9
// -------------------------------------------
10
// This file is part of eCos, the Embedded Configurable Operating System.
11
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
12
//
13
// eCos is free software; you can redistribute it and/or modify it under
14
// the terms of the GNU General Public License as published by the Free
15
// Software Foundation; either version 2 or (at your option) any later version.
16
//
17
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
18
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
19
// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
20
// for more details.
21
//
22
// You should have received a copy of the GNU General Public License along
23
// with eCos; if not, write to the Free Software Foundation, Inc.,
24
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
25
//
26
// As a special exception, if other files instantiate templates or use macros
27
// or inline functions from this file, or you compile this file and link it
28
// with other works to produce a work based on this file, this file does not
29
// by itself cause the resulting work to be covered by the GNU General Public
30
// License. However the source code for this file must still be made available
31
// in accordance with section (3) of the GNU General Public License.
32
//
33
// This exception does not invalidate any other reasons why a work based on
34
// this file might be covered by the GNU General Public License.
35
//
36
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
37
// at http://sources.redhat.com/ecos/ecos-license/
38
// -------------------------------------------
39
//####ECOSGPLCOPYRIGHTEND####
40
//=============================================================================
41
//#####DESCRIPTIONBEGIN####
42
//
43
// Author(s):   nickg, gthomas
44
// Contributors:nickg, gthomas
45
// Date:        1998-03-02
46
// Purpose:     HAL diagnostic output
47
// Description: Implementations of HAL diagnostic output support.
48
//
49
//####DESCRIPTIONEND####
50
//
51
//===========================================================================*/
52
 
53
#include <pkgconf/hal.h>
54
#include <pkgconf/hal_arm_pid.h>        // board specifics
55
 
56
#include <cyg/infra/cyg_type.h>         // base types
57
#include <cyg/infra/cyg_trac.h>         // tracing macros
58
#include <cyg/infra/cyg_ass.h>          // assertion macros
59
 
60
#include <cyg/hal/hal_arch.h>           // basic machine info
61
#include <cyg/hal/hal_intr.h>           // interrupt macros
62
#include <cyg/hal/hal_io.h>             // IO macros
63
#include <cyg/hal/hal_diag.h>
64
#include <cyg/hal/drv_api.h>
65
#include <cyg/hal/hal_if.h>             // interface API
66
#include <cyg/hal/hal_misc.h>           // Helper functions
67
 
68
/*---------------------------------------------------------------------------*/
69
/* From serial_16550.h */
70
#if CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD==9600
71
#define CYG_DEVICE_SERIAL_BAUD_MSB        0x00
72
#define CYG_DEVICE_SERIAL_BAUD_LSB        0x0C
73
#endif
74
#if CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD==19200
75
#define CYG_DEVICE_SERIAL_BAUD_MSB        0x00
76
#define CYG_DEVICE_SERIAL_BAUD_LSB        0x06
77
#endif
78
#if CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD==38400
79
#define CYG_DEVICE_SERIAL_BAUD_MSB        0x00
80
#define CYG_DEVICE_SERIAL_BAUD_LSB        0x03
81
#endif
82
#if CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD==115200
83
#define CYG_DEVICE_SERIAL_BAUD_MSB        0x00
84
#define CYG_DEVICE_SERIAL_BAUD_LSB        0x01
85
#endif
86
 
87
#ifndef CYG_DEVICE_SERIAL_BAUD_MSB
88
#error Missing/incorrect serial baud rate defined - CDL error?
89
#endif
90
 
91
// Define the serial registers.
92
#define CYG_DEV_RBR 0x00   // receiver buffer register, read, dlab = 0
93
#define CYG_DEV_THR 0x00   // transmitter holding register, write, dlab = 0
94
#define CYG_DEV_DLL 0x00   // divisor latch (LS), read/write, dlab = 1
95
#define CYG_DEV_IER 0x04   // interrupt enable register, read/write, dlab = 0
96
#define CYG_DEV_DLM 0x04   // divisor latch (MS), read/write, dlab = 1
97
#define CYG_DEV_IIR 0x08   // interrupt identification register, read, dlab = 0
98
#define CYG_DEV_FCR 0x08   // fifo control register, write, dlab = 0
99
#define CYG_DEV_LCR 0x0C   // line control register, read/write
100
#define CYG_DEV_MCR 0x10   // modem control register, read/write
101
#define CYG_DEV_LSR 0x14   // line status register, read
102
#define CYG_DEV_MSR 0x18   // modem status register, read
103
 
104
// Interrupt Enable Register
105
#define SIO_IER_RCV 0x01
106
#define SIO_IER_XMT 0x02
107
#define SIO_IER_LS  0x04
108
#define SIO_IER_MS  0x08
109
 
110
// The line status register bits.
111
#define SIO_LSR_DR      0x01            // data ready
112
#define SIO_LSR_OE      0x02            // overrun error
113
#define SIO_LSR_PE      0x04            // parity error
114
#define SIO_LSR_FE      0x08            // framing error
115
#define SIO_LSR_BI      0x10            // break interrupt
116
#define SIO_LSR_THRE    0x20            // transmitter holding register empty
117
#define SIO_LSR_TEMT    0x40            // transmitter register empty
118
#define SIO_LSR_ERR     0x80            // any error condition
119
 
120
// The modem status register bits.
121
#define SIO_MSR_DCTS  0x01              // delta clear to send
122
#define SIO_MSR_DDSR  0x02              // delta data set ready
123
#define SIO_MSR_TERI  0x04              // trailing edge ring indicator
124
#define SIO_MSR_DDCD  0x08              // delta data carrier detect
125
#define SIO_MSR_CTS   0x10              // clear to send
126
#define SIO_MSR_DSR   0x20              // data set ready
127
#define SIO_MSR_RI    0x40              // ring indicator
128
#define SIO_MSR_DCD   0x80              // data carrier detect
129
 
130
// The line control register bits.
131
#define SIO_LCR_WLS0   0x01             // word length select bit 0
132
#define SIO_LCR_WLS1   0x02             // word length select bit 1
133
#define SIO_LCR_STB    0x04             // number of stop bits
134
#define SIO_LCR_PEN    0x08             // parity enable
135
#define SIO_LCR_EPS    0x10             // even parity select
136
#define SIO_LCR_SP     0x20             // stick parity
137
#define SIO_LCR_SB     0x40             // set break
138
#define SIO_LCR_DLAB   0x80             // divisor latch access bit
139
 
140
// Modem Control Register
141
#define SIO_MCR_DTR 0x01
142
#define SIO_MCR_RTS 0x02
143
#define SIO_MCR_INT 0x08   // Enable interrupts
144
 
145
//-----------------------------------------------------------------------------
146
typedef struct {
147
    cyg_uint8* base;
148
    cyg_int32 msec_timeout;
149
    int isr_vector;
150
} channel_data_t;
151
 
152
//-----------------------------------------------------------------------------
153
 
154
static void
155
cyg_hal_plf_serial_init_channel(void* __ch_data)
156
{
157
    cyg_uint8* base = ((channel_data_t*)__ch_data)->base;
158
    cyg_uint8 lcr;
159
 
160
    // 8-1-no parity.
161
    HAL_WRITE_UINT8(base+CYG_DEV_LCR, SIO_LCR_WLS0 | SIO_LCR_WLS1);
162
 
163
    HAL_READ_UINT8(base+CYG_DEV_LCR, lcr);
164
    lcr |= SIO_LCR_DLAB;
165
    HAL_WRITE_UINT8(base+CYG_DEV_LCR, lcr);
166
    HAL_WRITE_UINT8(base+CYG_DEV_DLL, CYG_DEVICE_SERIAL_BAUD_LSB);
167
    HAL_WRITE_UINT8(base+CYG_DEV_DLM, CYG_DEVICE_SERIAL_BAUD_MSB);
168
    lcr &= ~SIO_LCR_DLAB;
169
    HAL_WRITE_UINT8(base+CYG_DEV_LCR, lcr);
170
    HAL_WRITE_UINT8(base+CYG_DEV_FCR, 0x07);  // Enable & clear FIFO
171
}
172
 
173
void
174
cyg_hal_plf_serial_putc(void *__ch_data, char c)
175
{
176
    cyg_uint8* base = ((channel_data_t*)__ch_data)->base;
177
    cyg_uint8 lsr;
178
    CYGARC_HAL_SAVE_GP();
179
 
180
    do {
181
        HAL_READ_UINT8(base+CYG_DEV_LSR, lsr);
182
    } while ((lsr & SIO_LSR_THRE) == 0);
183
 
184
    HAL_WRITE_UINT8(base+CYG_DEV_THR, c);
185
 
186
    CYGARC_HAL_RESTORE_GP();
187
}
188
 
189
static cyg_bool
190
cyg_hal_plf_serial_getc_nonblock(void* __ch_data, cyg_uint8* ch)
191
{
192
    cyg_uint8* base = ((channel_data_t*)__ch_data)->base;
193
    cyg_uint8 lsr;
194
 
195
    HAL_READ_UINT8(base+CYG_DEV_LSR, lsr);
196
    if ((lsr & SIO_LSR_DR) == 0)
197
        return false;
198
 
199
    HAL_READ_UINT8(base+CYG_DEV_RBR, *ch);
200
 
201
    return true;
202
}
203
 
204
cyg_uint8
205
cyg_hal_plf_serial_getc(void* __ch_data)
206
{
207
    cyg_uint8 ch;
208
    CYGARC_HAL_SAVE_GP();
209
 
210
    while(!cyg_hal_plf_serial_getc_nonblock(__ch_data, &ch));
211
 
212
    CYGARC_HAL_RESTORE_GP();
213
    return ch;
214
}
215
 
216
static channel_data_t pid_ser_channels[2] = {
217
    { (cyg_uint8*)0x0D800000, 1000, CYGNUM_HAL_INTERRUPT_SERIALA },
218
    { (cyg_uint8*)0x0D800020, 1000, CYGNUM_HAL_INTERRUPT_SERIALB }
219
};
220
 
221
static void
222
cyg_hal_plf_serial_write(void* __ch_data, const cyg_uint8* __buf,
223
                         cyg_uint32 __len)
224
{
225
    CYGARC_HAL_SAVE_GP();
226
 
227
    while(__len-- > 0)
228
        cyg_hal_plf_serial_putc(__ch_data, *__buf++);
229
 
230
    CYGARC_HAL_RESTORE_GP();
231
}
232
 
233
static void
234
cyg_hal_plf_serial_read(void* __ch_data, cyg_uint8* __buf, cyg_uint32 __len)
235
{
236
    CYGARC_HAL_SAVE_GP();
237
 
238
    while(__len-- > 0)
239
        *__buf++ = cyg_hal_plf_serial_getc(__ch_data);
240
 
241
    CYGARC_HAL_RESTORE_GP();
242
}
243
 
244
cyg_bool
245
cyg_hal_plf_serial_getc_timeout(void* __ch_data, cyg_uint8* ch)
246
{
247
    int delay_count;
248
    channel_data_t* chan = (channel_data_t*)__ch_data;
249
    cyg_bool res;
250
    CYGARC_HAL_SAVE_GP();
251
 
252
    delay_count = chan->msec_timeout * 10; // delay in .1 ms steps
253
 
254
    for(;;) {
255
        res = cyg_hal_plf_serial_getc_nonblock(__ch_data, ch);
256
        if (res || 0 == delay_count--)
257
            break;
258
 
259
        CYGACC_CALL_IF_DELAY_US(100);
260
    }
261
 
262
    CYGARC_HAL_RESTORE_GP();
263
    return res;
264
}
265
 
266
static int
267
cyg_hal_plf_serial_control(void *__ch_data, __comm_control_cmd_t __func, ...)
268
{
269
    static int irq_state = 0;
270
    channel_data_t* chan = (channel_data_t*)__ch_data;
271
    int ret = 0;
272
    CYGARC_HAL_SAVE_GP();
273
 
274
    switch (__func) {
275
    case __COMMCTL_IRQ_ENABLE:
276
        irq_state = 1;
277
 
278
        HAL_WRITE_UINT8(chan->base+CYG_DEV_IER, SIO_IER_RCV);
279
        HAL_WRITE_UINT8(chan->base+CYG_DEV_MCR, SIO_MCR_INT|SIO_MCR_DTR|SIO_MCR_RTS);
280
 
281
        HAL_INTERRUPT_UNMASK(chan->isr_vector);
282
        break;
283
    case __COMMCTL_IRQ_DISABLE:
284
        ret = irq_state;
285
        irq_state = 0;
286
 
287
        HAL_WRITE_UINT8(chan->base+CYG_DEV_IER, 0);
288
 
289
        HAL_INTERRUPT_MASK(chan->isr_vector);
290
        break;
291
    case __COMMCTL_DBG_ISR_VECTOR:
292
        ret = chan->isr_vector;
293
        break;
294
    case __COMMCTL_SET_TIMEOUT:
295
    {
296
        va_list ap;
297
 
298
        va_start(ap, __func);
299
 
300
        ret = chan->msec_timeout;
301
        chan->msec_timeout = va_arg(ap, cyg_uint32);
302
 
303
        va_end(ap);
304
    }
305
    default:
306
        break;
307
    }
308
    CYGARC_HAL_RESTORE_GP();
309
    return ret;
310
}
311
 
312
static int
313
cyg_hal_plf_serial_isr(void *__ch_data, int* __ctrlc,
314
                       CYG_ADDRWORD __vector, CYG_ADDRWORD __data)
315
{
316
    int res = 0;
317
    channel_data_t* chan = (channel_data_t*)__ch_data;
318
    char c;
319
    cyg_uint8 lsr;
320
    CYGARC_HAL_SAVE_GP();
321
 
322
    cyg_drv_interrupt_acknowledge(chan->isr_vector);
323
 
324
    *__ctrlc = 0;
325
    HAL_READ_UINT8(chan->base+CYG_DEV_LSR, lsr);
326
    if ( (lsr & SIO_LSR_DR) != 0 ) {
327
 
328
        HAL_READ_UINT8(chan->base+CYG_DEV_RBR, c);
329
        if( cyg_hal_is_break( &c , 1 ) )
330
            *__ctrlc = 1;
331
 
332
        res = CYG_ISR_HANDLED;
333
    }
334
 
335
    CYGARC_HAL_RESTORE_GP();
336
    return res;
337
}
338
 
339
static void
340
cyg_hal_plf_serial_init(void)
341
{
342
    hal_virtual_comm_table_t* comm;
343
    int cur = CYGACC_CALL_IF_SET_CONSOLE_COMM(CYGNUM_CALL_IF_SET_COMM_ID_QUERY_CURRENT);
344
 
345
    // Disable interrupts.
346
    HAL_INTERRUPT_MASK(pid_ser_channels[0].isr_vector);
347
    HAL_INTERRUPT_MASK(pid_ser_channels[1].isr_vector);
348
 
349
    // Init channels
350
    cyg_hal_plf_serial_init_channel(&pid_ser_channels[0]);
351
    cyg_hal_plf_serial_init_channel(&pid_ser_channels[1]);
352
 
353
    // Setup procs in the vector table
354
 
355
    // Set channel 0
356
    CYGACC_CALL_IF_SET_CONSOLE_COMM(0);
357
    comm = CYGACC_CALL_IF_CONSOLE_PROCS();
358
    CYGACC_COMM_IF_CH_DATA_SET(*comm, &pid_ser_channels[0]);
359
    CYGACC_COMM_IF_WRITE_SET(*comm, cyg_hal_plf_serial_write);
360
    CYGACC_COMM_IF_READ_SET(*comm, cyg_hal_plf_serial_read);
361
    CYGACC_COMM_IF_PUTC_SET(*comm, cyg_hal_plf_serial_putc);
362
    CYGACC_COMM_IF_GETC_SET(*comm, cyg_hal_plf_serial_getc);
363
    CYGACC_COMM_IF_CONTROL_SET(*comm, cyg_hal_plf_serial_control);
364
    CYGACC_COMM_IF_DBG_ISR_SET(*comm, cyg_hal_plf_serial_isr);
365
    CYGACC_COMM_IF_GETC_TIMEOUT_SET(*comm, cyg_hal_plf_serial_getc_timeout);
366
 
367
    // Set channel 1
368
    CYGACC_CALL_IF_SET_CONSOLE_COMM(1);
369
    comm = CYGACC_CALL_IF_CONSOLE_PROCS();
370
    CYGACC_COMM_IF_CH_DATA_SET(*comm, &pid_ser_channels[1]);
371
    CYGACC_COMM_IF_WRITE_SET(*comm, cyg_hal_plf_serial_write);
372
    CYGACC_COMM_IF_READ_SET(*comm, cyg_hal_plf_serial_read);
373
    CYGACC_COMM_IF_PUTC_SET(*comm, cyg_hal_plf_serial_putc);
374
    CYGACC_COMM_IF_GETC_SET(*comm, cyg_hal_plf_serial_getc);
375
    CYGACC_COMM_IF_CONTROL_SET(*comm, cyg_hal_plf_serial_control);
376
    CYGACC_COMM_IF_DBG_ISR_SET(*comm, cyg_hal_plf_serial_isr);
377
    CYGACC_COMM_IF_GETC_TIMEOUT_SET(*comm, cyg_hal_plf_serial_getc_timeout);
378
 
379
    // Restore original console
380
    CYGACC_CALL_IF_SET_CONSOLE_COMM(cur);
381
}
382
 
383
void
384
cyg_hal_plf_comms_init(void)
385
{
386
    static int initialized = 0;
387
 
388
    if (initialized)
389
        return;
390
 
391
    initialized = 1;
392
 
393
    cyg_hal_plf_serial_init();
394
}
395
 
396
/*---------------------------------------------------------------------------*/
397
 
398
#ifdef CYGHWR_HAL_ARM_PID_DIAG_LEDS
399
// Control the LEDs PP0-PP3. This requires the jumpers on pins 9-16 to
400
// be set on LK11, thus preventing the use of the parallel port.
401
 
402
#define CYG_DEVICE_PARALLEL_DATA 0x0d800040
403
 
404
void
405
hal_diag_led(int n)
406
{
407
    HAL_WRITE_UINT8(CYG_DEVICE_PARALLEL_DATA, (n & 0xf) << 4);
408
}
409
#endif // CYGHWR_HAL_ARM_PID_DIAG_LEDS
410
 
411
 
412
//=============================================================================
413
// Compatibility with older stubs
414
//=============================================================================
415
 
416
#ifndef CYGSEM_HAL_VIRTUAL_VECTOR_DIAG
417
 
418
#ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
419
#include <cyg/hal/hal_stub.h>           // cyg_hal_gdb_interrupt
420
#endif
421
 
422
#if CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL==0
423
// This is the base address of the A-channel
424
#define CYG_DEV_SERIAL_BASE      0x0D800000
425
#define CYG_DEVICE_SERIAL_INT    CYGNUM_HAL_INTERRUPT_SERIALA
426
#else
427
// This is the base address of the B-channel
428
#define CYG_DEV_SERIAL_BASE      0x0D800020
429
#define CYG_DEVICE_SERIAL_INT    CYGNUM_HAL_INTERRUPT_SERIALB
430
#endif
431
 
432
static channel_data_t pid_ser_channel = {
433
    (cyg_uint8*)CYG_DEV_SERIAL_BASE, 0, 0
434
};
435
 
436
// Assumption: all diagnostic output must be GDB packetized unless this is a ROM (i.e.
437
// totally stand-alone) system.
438
 
439
#if defined(CYG_HAL_STARTUP_ROM) || !defined(CYGDBG_HAL_DIAG_TO_DEBUG_CHAN)
440
#define HAL_DIAG_USES_HARDWARE
441
#endif
442
 
443
#ifndef HAL_DIAG_USES_HARDWARE
444
#if (CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL != CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL)
445
#define HAL_DIAG_USES_HARDWARE
446
#endif
447
#endif
448
 
449
#ifdef HAL_DIAG_USES_HARDWARE
450
 
451
void hal_diag_init(void)
452
{
453
    static int init = 0;
454
    char *msg = "\n\rARM eCos\n\r";
455
 
456
    if (init++) return;
457
 
458
    cyg_hal_plf_serial_init_channel(&pid_ser_channel);
459
 
460
    while (*msg) cyg_hal_plf_serial_putc(&pid_ser_channel, *msg++);
461
}
462
 
463
#ifdef DEBUG_DIAG
464
#if defined(CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS)
465
#define DIAG_BUFSIZE 32
466
#else
467
#define DIAG_BUFSIZE 2048
468
#endif
469
static char diag_buffer[DIAG_BUFSIZE];
470
static int diag_bp = 0;
471
#endif
472
 
473
void hal_diag_write_char(char c)
474
{
475
    hal_diag_init();
476
 
477
    cyg_hal_plf_serial_putc(&pid_ser_channel, c);
478
 
479
#ifdef DEBUG_DIAG
480
    diag_buffer[diag_bp++] = c;
481
    if (diag_bp == DIAG_BUFSIZE) diag_bp = 0;
482
#endif
483
}
484
 
485
void hal_diag_read_char(char *c)
486
{
487
    *c = cyg_hal_plf_serial_getc(&pid_ser_channel);
488
}
489
 
490
#else // HAL_DIAG relies on GDB
491
 
492
// Initialize diag port - assume GDB channel is already set up
493
void hal_diag_init(void)
494
{
495
    if (0) cyg_hal_plf_serial_init_channel(&pid_ser_channel); // avoid warning
496
}
497
 
498
// Actually send character down the wire
499
static void
500
hal_diag_write_char_serial(char c)
501
{
502
    hal_diag_init();
503
 
504
    cyg_hal_plf_serial_putc(&pid_ser_channel, c);
505
}
506
 
507
static bool
508
hal_diag_read_serial(char *c)
509
{
510
    long timeout = 1000000000;  // A long time...
511
    while (!cyg_hal_plf_serial_getc_nonblock(&pid_ser_channel, c))
512
        if (0 == --timeout) return false;
513
 
514
    return true;
515
}
516
 
517
void
518
hal_diag_read_char(char *c)
519
{
520
    while (!hal_diag_read_serial(c)) ;
521
}
522
 
523
void
524
hal_diag_write_char(char c)
525
{
526
    static char line[100];
527
    static int pos = 0;
528
 
529
    // No need to send CRs
530
    if( c == '\r' ) return;
531
 
532
    line[pos++] = c;
533
 
534
    if( c == '\n' || pos == sizeof(line) )
535
    {
536
        CYG_INTERRUPT_STATE old;
537
 
538
        // Disable interrupts. This prevents GDB trying to interrupt us
539
        // while we are in the middle of sending a packet. The serial
540
        // receive interrupt will be seen when we re-enable interrupts
541
        // later.
542
 
543
#ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
544
        CYG_HAL_GDB_ENTER_CRITICAL_IO_REGION(old);
545
#else
546
        HAL_DISABLE_INTERRUPTS(old);
547
#endif
548
 
549
        while(1)
550
        {
551
            static char hex[] = "0123456789ABCDEF";
552
            cyg_uint8 csum = 0;
553
            int i;
554
            char c1;
555
 
556
            hal_diag_write_char_serial('$');
557
            hal_diag_write_char_serial('O');
558
            csum += 'O';
559
            for( i = 0; i < pos; i++ )
560
            {
561
                char ch = line[i];
562
                char h = hex[(ch>>4)&0xF];
563
                char l = hex[ch&0xF];
564
                hal_diag_write_char_serial(h);
565
                hal_diag_write_char_serial(l);
566
                csum += h;
567
                csum += l;
568
            }
569
            hal_diag_write_char_serial('#');
570
            hal_diag_write_char_serial(hex[(csum>>4)&0xF]);
571
            hal_diag_write_char_serial(hex[csum&0xF]);
572
 
573
            // Wait for the ACK character '+' from GDB here and handle
574
            // receiving a ^C instead.  This is the reason for this clause
575
            // being a loop.
576
            if (!hal_diag_read_serial(&c1))
577
                continue;   // No response - try sending packet again
578
 
579
            if( c1 == '+' )
580
                break;              // a good acknowledge
581
 
582
#ifdef CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT
583
            cyg_drv_interrupt_acknowledge(CYG_DEVICE_SERIAL_INT);
584
            if( c1 == 3 ) {
585
                // Ctrl-C: breakpoint.
586
                cyg_hal_gdb_interrupt ((target_register_t)__builtin_return_address(0));
587
                break;
588
            }
589
#endif
590
            // otherwise, loop round again
591
        }
592
 
593
        pos = 0;
594
 
595
        // And re-enable interrupts
596
#ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
597
        CYG_HAL_GDB_LEAVE_CRITICAL_IO_REGION(old);
598
#else
599
        HAL_RESTORE_INTERRUPTS(old);
600
#endif
601
 
602
    }
603
}
604
#endif
605
 
606
#endif // CYGSEM_HAL_VIRTUAL_VECTOR_DIAG
607
 
608
/*---------------------------------------------------------------------------*/
609
/* End of hal_diag.c */

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