OpenCores
URL https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk

Subversion Repositories openrisc_2011-10-31

[/] [openrisc/] [trunk/] [rtos/] [ecos-2.0/] [packages/] [hal/] [arm/] [pid/] [v2_0/] [src/] [pid_misc.c] - Blame information for rev 174

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 27 unneback
//==========================================================================
2
//
3
//      pid_misc.c
4
//
5
//      HAL misc board support code for ARM PID7
6
//
7
//==========================================================================
8
//####ECOSGPLCOPYRIGHTBEGIN####
9
// -------------------------------------------
10
// This file is part of eCos, the Embedded Configurable Operating System.
11
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
12
//
13
// eCos is free software; you can redistribute it and/or modify it under
14
// the terms of the GNU General Public License as published by the Free
15
// Software Foundation; either version 2 or (at your option) any later version.
16
//
17
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
18
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
19
// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
20
// for more details.
21
//
22
// You should have received a copy of the GNU General Public License along
23
// with eCos; if not, write to the Free Software Foundation, Inc.,
24
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
25
//
26
// As a special exception, if other files instantiate templates or use macros
27
// or inline functions from this file, or you compile this file and link it
28
// with other works to produce a work based on this file, this file does not
29
// by itself cause the resulting work to be covered by the GNU General Public
30
// License. However the source code for this file must still be made available
31
// in accordance with section (3) of the GNU General Public License.
32
//
33
// This exception does not invalidate any other reasons why a work based on
34
// this file might be covered by the GNU General Public License.
35
//
36
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
37
// at http://sources.redhat.com/ecos/ecos-license/
38
// -------------------------------------------
39
//####ECOSGPLCOPYRIGHTEND####
40
//==========================================================================
41
//#####DESCRIPTIONBEGIN####
42
//
43
// Author(s):    gthomas
44
// Contributors: gthomas
45
// Date:         1999-02-20
46
// Purpose:      HAL board support
47
// Description:  Implementations of HAL board interfaces
48
//
49
//####DESCRIPTIONEND####
50
//
51
//===========================================================================*/
52
 
53
#include <pkgconf/hal.h>
54
 
55
#include <cyg/infra/cyg_type.h>         // base types
56
#include <cyg/infra/cyg_trac.h>         // tracing macros
57
#include <cyg/infra/cyg_ass.h>          // assertion macros
58
 
59
#include <cyg/hal/hal_io.h>             // IO macros
60
#include <cyg/hal/hal_arch.h>           // Register state info
61
#include <cyg/hal/hal_diag.h>
62
#include <cyg/hal/hal_intr.h>           // necessary?
63
#include <cyg/hal/hal_if.h>             // calling interface
64
 
65
/*------------------------------------------------------------------------*/
66
// On-board timer
67
/*------------------------------------------------------------------------*/
68
 
69
// Timer registers
70
#define CYG_DEVICE_TIMER1_BASE   0x0A800020
71
#define CYG_DEVICE_TIMER1_LOAD \
72
    ((volatile cyg_uint32 *) (CYG_DEVICE_TIMER1_BASE + 0x00))
73
    // Load value, read/write
74
#define CYG_DEVICE_TIMER1_CURRENT \
75
    ((volatile cyg_uint32 *) (CYG_DEVICE_TIMER1_BASE + 0x04))
76
    // Current value, read
77
#define CYG_DEVICE_TIMER1_CONTROL \
78
    ((volatile cyg_uint32 *) (CYG_DEVICE_TIMER1_BASE + 0x08))
79
    // Control register, read/write
80
#define CYG_DEVICE_TIMER1_CLEAR \
81
    ((volatile cyg_uint32 *) (CYG_DEVICE_TIMER1_BASE + 0x0C))
82
    // Clears interrrupt, write only
83
 
84
#define CYG_DEVICE_TIMER_BASE   0x0A800020
85
#define CYG_DEVICE_TIMER_LOAD \
86
    ((volatile cyg_uint32 *) (CYG_DEVICE_TIMER_BASE + 0x00))
87
    // Load value, read/write
88
#define CYG_DEVICE_TIMER_CURRENT \
89
    ((volatile cyg_uint32 *) (CYG_DEVICE_TIMER_BASE + 0x04))
90
    // Current value, read
91
#define CYG_DEVICE_TIMER_CONTROL \
92
    ((volatile cyg_uint32 *) (CYG_DEVICE_TIMER_BASE + 0x08))
93
    // Control register, read/write
94
#define CYG_DEVICE_TIMER_CLEAR \
95
    ((volatile cyg_uint32 *) (CYG_DEVICE_TIMER_BASE + 0x0C))
96
    // Clears interrrupt, write only
97
 
98
// Clock/timer control register
99
#define CTL_ENABLE      0x80            // Bit   7: 1 - counter enabled
100
#define CTL_DISABLE     0x00            //          0 - counter disabled
101
#define CTL_FREERUN     0x00            // Bit   6: 0 - free running counter
102
#define CTL_PERIODIC    0x40            //          1 - periodic timer mode
103
#define CTL_SCALE_1     0x00            // Bits 32: 00 - Scale clock by 1
104
#define CTL_SCALE_16    0x04            //          01 - Scale by 16
105
#define CTL_SCALE_256   0x08            //          10 - Scale by 256
106
                                        //               12.8us/tick
107
 
108
// Interrupt controller registers
109
#define CYG_DEVICE_ICTL_BASE    0x0A000000
110
#define CYG_DEVICE_IRQ_Status \
111
    ((volatile cyg_uint32 *) (CYG_DEVICE_ICTL_BASE + 0x00))
112
    // Current status, read only
113
#define CYG_DEVICE_IRQ_Enable \
114
    ((volatile cyg_uint32 *) (CYG_DEVICE_ICTL_BASE + 0x08))
115
    // Enable status, read only
116
#define CYG_DEVICE_IRQ_EnableSet \
117
    ((volatile cyg_uint32 *) (CYG_DEVICE_ICTL_BASE + 0x08))
118
    // Enable (1's only), write only
119
#define CYG_DEVICE_IRQ_EnableClear \
120
    ((volatile cyg_uint32 *) (CYG_DEVICE_ICTL_BASE + 0x0C))
121
    // Disable (1's only), write only
122
 
123
static cyg_uint32 _period;
124
 
125
void hal_clock_initialize(cyg_uint32 period)
126
{
127
    //diag_init();  diag_printf("%s(%d)\n", __PRETTY_FUNCTION__, period);
128
    //diag_printf("psr = %x\n", psr());
129
    HAL_WRITE_UINT32(CYG_DEVICE_TIMER_CONTROL, CTL_DISABLE);    // Turn off
130
    HAL_WRITE_UINT32(CYG_DEVICE_TIMER_LOAD, period);
131
    HAL_WRITE_UINT32(CYG_DEVICE_TIMER_CONTROL,
132
                     CTL_ENABLE | CTL_PERIODIC | CTL_SCALE_16);
133
    _period = period;
134
}
135
 
136
void hal_clock_reset(cyg_uint32 vector, cyg_uint32 period)
137
{
138
    //diag_init();  diag_printf("%s\n", __PRETTY_FUNCTION__);
139
    HAL_WRITE_UINT32(CYG_DEVICE_TIMER_CLEAR, 0);
140
    _period = period;
141
}
142
 
143
void hal_clock_read(cyg_uint32 *pvalue)
144
{
145
    cyg_uint32 value;
146
//    diag_init();  diag_printf("%s\n", __PRETTY_FUNCTION__);
147
    HAL_READ_UINT32(CYG_DEVICE_TIMER_CURRENT, value);
148
    value &= 0xFFFF;
149
    *pvalue = _period - (value & 0xFFFF);   // Note: counter is only 16 bits
150
                                            //       and decreases
151
}
152
 
153
// -------------------------------------------------------------------------
154
//
155
// Delay for some number of micro-seconds
156
//
157
void hal_delay_us(cyg_int32 usecs)
158
{
159
    cyg_uint32 value;
160
    cyg_uint64 ticks = ((usecs*CYGNUM_HAL_RTC_PERIOD*CYGNUM_HAL_RTC_DENOMINATOR)/1000000);
161
 
162
    HAL_WRITE_UINT32(CYG_DEVICE_TIMER1_CONTROL, CTL_DISABLE);    // Turn off
163
    HAL_WRITE_UINT32(CYG_DEVICE_TIMER1_LOAD, ticks);
164
    HAL_WRITE_UINT32(CYG_DEVICE_TIMER1_CONTROL,
165
                     CTL_ENABLE | CTL_FREERUN | CTL_SCALE_16);
166
 
167
    // Wait for timer to underflow
168
    do {
169
        HAL_READ_UINT32(CYG_DEVICE_TIMER_CURRENT, value);
170
        value &= 0xFFFF;
171
    } while (value < 0x7fff);
172
 
173
    HAL_WRITE_UINT32(CYG_DEVICE_TIMER1_CONTROL, CTL_DISABLE);    // Turn off
174
}
175
 
176
// -------------------------------------------------------------------------
177
 
178
void hal_hardware_init(void)
179
{
180
    // Any hardware/platform initialization that needs to be done.
181
    HAL_WRITE_UINT32(CYG_DEVICE_IRQ_EnableClear, 0xFFFF); // Clear all
182
                                                         // interrupt sources
183
    // Set up eCos/ROM interfaces
184
    hal_if_init();
185
}
186
 
187
//
188
// This routine is called to respond to a hardware interrupt (IRQ).  It
189
// should interrogate the hardware and return the IRQ vector number.
190
 
191
int hal_IRQ_handler(void)
192
{
193
    // Do hardware-level IRQ handling
194
    int irq_status, vector;
195
    HAL_READ_UINT32(CYG_DEVICE_IRQ_Status, irq_status);
196
    //diag_init();  diag_printf("%s, status: %x\n", __PRETTY_FUNCTION__, irq_status); 
197
    for (vector = 1;  vector < 16;  vector++) {
198
        if (irq_status & (1<<vector)) return vector;
199
    }
200
    return CYGNUM_HAL_INTERRUPT_NONE; // This shouldn't happen!
201
}
202
 
203
//
204
// Interrupt control
205
//
206
 
207
void hal_interrupt_mask(int vector)
208
{
209
    //diag_init();  diag_printf("%s(%d)\n", __PRETTY_FUNCTION__, vector);
210
    HAL_WRITE_UINT32(CYG_DEVICE_IRQ_EnableClear, 1<<vector);
211
}
212
 
213
#if 0
214
void hal_interrupt_status(void)
215
{
216
    int irq_status, irq_enable, timer_status, timer_value, timer_load;
217
    HAL_READ_UINT32(CYG_DEVICE_IRQ_Status, irq_status);
218
    HAL_READ_UINT32(CYG_DEVICE_IRQ_Enable, irq_enable);
219
    HAL_READ_UINT32(CYG_DEVICE_TIMER_LOAD, timer_load);
220
    HAL_READ_UINT32(CYG_DEVICE_TIMER_CURRENT, timer_value);
221
    HAL_READ_UINT32(CYG_DEVICE_TIMER_CONTROL, timer_status);
222
    diag_printf("Interrupt: IRQ: %x.%x, TIMER: %x.%x.%x, psr: %x\n",
223
                irq_status, irq_enable, timer_status, timer_value,
224
                timer_load, psr());
225
}
226
#endif
227
 
228
void hal_interrupt_unmask(int vector)
229
{
230
    //diag_init();  diag_printf("%s(%d)\n", __PRETTY_FUNCTION__, vector);
231
    HAL_WRITE_UINT32(CYG_DEVICE_IRQ_EnableSet, 1<<vector);
232
}
233
 
234
void hal_interrupt_acknowledge(int vector)
235
{
236
    //diag_init();  diag_printf("%s(%d)\n", __PRETTY_FUNCTION__, vector);
237
}
238
 
239
void hal_interrupt_configure(int vector, int level, int up)
240
{
241
    //diag_init();  diag_printf("%s(%d,%d,%d)\n", __PRETTY_FUNCTION__, vector, level, up);
242
}
243
 
244
void hal_interrupt_set_level(int vector, int level)
245
{
246
    //diag_init();  diag_printf("%s(%d,%d)\n", __PRETTY_FUNCTION__, vector, level);
247
}
248
 
249
void hal_show_IRQ(int vector, int data, int handler)
250
{
251
    //    diag_printf("IRQ - vector: %x, data: %x, handler: %x\n", vector, data, handler);
252
}
253
 
254
/*---------------------------------------------------------------------------*/
255
/* End of hal_misc.c */

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.