OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [rtos/] [ecos-2.0/] [packages/] [hal/] [arm/] [sa11x0/] [assabet/] [v2_0/] [include/] [pkgconf/] [mlt_arm_sa11x0_assabet_ram.ldi] - Blame information for rev 27

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 27 unneback
// eCos memory layout - Fri Oct 20 05:56:24 2000
2
 
3
// This is a generated file - do not edit
4
 
5
#include 
6
 
7
MEMORY
8
{
9
    ram : ORIGIN = 0, LENGTH = 0x2000000
10
}
11
 
12
SECTIONS
13
{
14
    SECTIONS_BEGIN
15
    SECTION_fixed_vectors (ram, 0x20, LMA_EQ_VMA)
16
    SECTION_rom_vectors (ram, 0x20000, LMA_EQ_VMA)
17
    SECTION_text (ram, ALIGN (0x4), LMA_EQ_VMA)
18
    SECTION_fini (ram, ALIGN (0x4), LMA_EQ_VMA)
19
    SECTION_rodata (ram, ALIGN (0x4), LMA_EQ_VMA)
20
    SECTION_rodata1 (ram, ALIGN (0x4), LMA_EQ_VMA)
21
    SECTION_fixup (ram, ALIGN (0x4), LMA_EQ_VMA)
22
    SECTION_gcc_except_table (ram, ALIGN (0x4), LMA_EQ_VMA)
23
    SECTION_data (ram, ALIGN (0x4), LMA_EQ_VMA)
24
    SECTION_bss (ram, ALIGN (0x4), LMA_EQ_VMA)
25
    CYG_LABEL_DEFN(__heap1) = ALIGN (0x8);
26
    SECTIONS_END
27
}

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.