OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [rtos/] [ecos-2.0/] [packages/] [hal/] [arm/] [sa11x0/] [nano/] [v2_0/] [ChangeLog] - Blame information for rev 587

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 27 unneback
2003-02-13  Patrick Doyle  
2
        * src/nano_misc.c: Replaced explicit prototype of memset with
3
        #include .
4
 
5
2002-08-12  Mark Salter  
6
 
7
        * misc/redboot_POST.ecm: Remove CYGSEM_REDBOOT_ARM_LINUX_BOOT.
8
        * misc/redboot_RAM.ecm: Ditto.
9
 
10
2002-05-14  Jesper Skov  
11
 
12
        * src/nano_misc.c: Fixed warning.
13
 
14
2002-05-07  Gary Thomas  
15
 
16
        * cdl/hal_arm_sa11x0_nano.cdl:
17
        Standardize CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_DEFAULT usage.
18
 
19
2002-03-06  Jesper Skov  
20
 
21
        * misc/redboot_RAM.ecm: Updated. Added zlib.
22
        * misc/redboot_ROM.ecm: Same.
23
 
24
2002-01-30  Jonathan Larmour  
25
 
26
        * include/nano.h (HAL_PCI_DO_CONFIG_ACCESS): If requesting vendor
27
        config, check it isn't 0 or 256 which would be bogus - instead
28
        this indicates the device is absent, e.g. the second eth controller
29
        that is found on the commEngine, but not on the nanoEngine.
30
 
31
2002-01-28  Jesper Skov  
32
 
33
        * include/plf_io.h: Added.
34
 
35
        * cdl/hal_arm_sa11x0_nano.cdl: Remove explicit plf_io.h
36
        declaration.
37
 
38
2001-05-02  Hugo Tyson  
39
 
40
        * src/nano_misc.c (hal_mmu_init): Set up PCI memory in the new
41
        location, where it will not already be mapped by the default
42
        layout.  This requires "stealing" RAM from the linear layout.
43
        It's done this way so that a RAM app will work OK atop an
44
        old-style RedBoot with the old PCI window area set up.
45
        (hal_arm_mem_real_region_top): Better comments, and a safety
46
        check; do not repeat the test for boundary movement.
47
 
48
        * include/pkgconf/mlt_arm_sa11x0_nano_ram.ldi:
49
        * include/pkgconf/mlt_arm_sa11x0_nano_ram.h:
50
        * include/pkgconf/mlt_arm_sa11x0_nano_ram.mlt:
51
        * include/pkgconf/mlt_arm_sa11x0_nano_post.ldi:
52
        * include/pkgconf/mlt_arm_sa11x0_nano_post.h:
53
        * include/pkgconf/mlt_arm_sa11x0_nano_post.mlt:
54
        Add "fixed" region to contain PCI window at 0xfa00000 (250Mb),
55
        well away from normal memory.  Adjust ram region size to 15Mb - a
56
        smaller possible memory installation, with the 1Mb default PCI
57
        window removed.
58
 
59
2001-04-27  Jonathan Larmour  
60
 
61
        * cdl/hal_arm_sa11x0_nano.cdl: Remove redundant -Wl,-N from link flags
62
 
63
2001-04-12  Hugo Tyson  
64
 
65
        * src/nano_misc.c (hal_arm_mem_real_region_top): Also report
66
        variants on the CYGMEM_SECTION_heap1 as described by default.
67
        This is ugly, but necessary, else the heap tries to use memory
68
        that is not installed.  Oh, for a proper MLT!
69
 
70
2001-04-02  Hugo Tyson  
71
 
72
        * misc/readme.txt: Update the readme to reflect more info about
73
        using the nano target.
74
 
75
2001-03-29  Hugo Tyson  
76
 
77
        * src/nano_misc.c (hal_mmu_init): Find the real physical address
78
        for mapping the uncacheable, unbufferable PCI window - it might be
79
        various places depending on what SDRAMs are installed.
80
 
81
2001-03-14  Hugo Tyson  
82
 
83
        * include/nano.h (HAL_PCI_INIT): Disconnect the two ethernet
84
        devices from the PCI bus during init so that we can re-scan during
85
        startup regardless of what happened before - such as
86
        network-enabled RedBoot doing the same setup already.
87
 
88
        * misc/redboot_POST.ecm:
89
        * misc/redboot_RAM.ecm:
90
        Enable package CYGPKG_IO_ETH_DRIVERS so that RedBoot is network
91
        capable.  Disable CYGPKG_DEVS_ETH_ARM_NANO_ETH1 so that it uses
92
        only the first ether device.  Tidy some comments and whitespace.
93
 
94
2001-03-08  Jesper Skov  
95
 
96
        * cdl/hal_arm_sa11x0_nano.cdl:  Removed
97
        CYGINT_HAL_VIRTUAL_VECTOR_SUPPORT_GUARANTEED which is now the
98
        default.
99
 
100
2001-03-01  Hugo Tyson  
101
 
102
        * include/pkgconf/mlt_arm_sa11x0_nano_post.h:
103
        * include/pkgconf/mlt_arm_sa11x0_nano_post.ldi:
104
        * include/pkgconf/mlt_arm_sa11x0_nano_post.mlt:
105
        * include/pkgconf/mlt_arm_sa11x0_nano_ram.h:
106
        * include/pkgconf/mlt_arm_sa11x0_nano_ram.ldi:
107
        * include/pkgconf/mlt_arm_sa11x0_nano_ram.mlt:
108
        Add MLT definition of PCI window.
109
        I chose 0x1e00000 ie. megabyte 30 because I believe
110
        megabyte 31 is used by RedBoot for buffers or stacks.
111
 
112
        * include/nano.h: Take external MLT definition of PCI window for
113
        defining BASE, SIZE symbols.  Set the interrupts on GPIO0 and
114
        GPIO1 to be falling-edge in HAL_PCI_INIT().  Don't define any of
115
        this unless CYGPKG_IO_PCI and not assembler.
116
 
117
        * src/nano_misc.c (hal_mmu_init): Take external MLT definition of
118
        PCI window.  Also define and initialize an int holding the real
119
        address of the PCI window, if CYGPKG_IO_PCI.
120
 
121
2001-02-28  Hugo Tyson  
122
 
123
        * include/plf_mmap.h (HAL_VIRT_TO_PHYS_ADDRESS): [et al] Use
124
        variant HAL routines which scan the true memory map installed.
125
        This is necessary for dealing with eg. PCI window - also future
126
        similar targets with different physical memory arrangements,
127
 
128
        * src/nano_misc.c (plf_hardware_init): Perform MMU initialization
129
        even in RAM startup - so that different configurations of
130
        ROM(RedBoot) and RAM app can work together.
131
        (hal_mmu_init): Perform partial initialization when in RAM startup
132
        - so that ROM settings can be overridden eg. for PCI non-cacheable
133
        memory windows and the like.  [Incomplete initial version.]
134
 
135
        * include/nano.h (HAL_PCI_INIT): Implement this and all its mates,
136
        ie. a PCI device driver for the nanoBridge and *very specifically*
137
        its two attached i82559s only - it's by no means general, because
138
        it's not a proper implementation of a PCI bridge.
139
 
140
2001-02-22  Hugo Tyson  
141
 
142
        * misc/redboot_POSTecm:
143
        * misc/redboot_RAM.ecm: add configuration of the Flash Image
144
        System initialization in RedBoot.
145
 
146
2001-02-20  Hugo Tyson  
147
 
148
        * cdl/hal_arm_sa11x0_nano.cdl: New CDL describing serial
149
        ports - CYGHWR_HAL_ARM_SA11X0_UART1,3.
150
 
151
        * cdl/hal_arm_sa11x0_nano.cdl: Also changed the default baud rates
152
        to 38400, having realized that the other port works just fine too.
153
        So you can put your serial line on the non-BSE port for normal
154
        work and not be hassled by out-of-time characters over reset.
155
 
156
2001-02-15  Hugo Tyson  
157
 
158
        * misc/redboot_POST.ecm:
159
        * misc/redboot_RAM.ecm:
160
        Add CYGPKG_IO_FLASH for RedBoot builds now that flash driver
161
        exists.   CYGPKG_DEVS_FLASH_NANO + CYGPKG_DEVS_FLASH_STRATA
162
 
163
2001-02-14  Hugo Tyson  
164
 
165
        * include/hal_platform_setup.h: Clean up debug and cache hacks to
166
        get it limping along.  Import proper value (as read from system
167
        regs) to SDRAM controller setup - in case true ROM startup is ever
168
        used.
169
 
170
        * src/nano_misc.c (hal_arm_mem_real_region_top): Add.  Support
171
        hal_dram_size.
172
        (hal_mmu_init): Add a SDRAM sizer like others we have.  Just in
173
        case.  Deals with 32Mb sized parts also.
174
 
175
        * cdl/hal_arm_sa11x0_nano.cdl: implements
176
        CYGINT_HAL_ARM_MEM_REAL_REGION_TOP
177
 
178
2001-02-14  Hugo Tyson  
179
 
180
        * hal/arm/sa11x0/nano: New package, based on Assabet
181
        HAL.  This is the nanoEngine from Bright Star Engineering; an
182
        SA1110 CPU + 2x i82559 ethernets.
183
 
184
//===========================================================================
185
//####ECOSGPLCOPYRIGHTBEGIN####
186
// -------------------------------------------
187
// This file is part of eCos, the Embedded Configurable Operating System.
188
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
189
//
190
// eCos is free software; you can redistribute it and/or modify it under
191
// the terms of the GNU General Public License as published by the Free
192
// Software Foundation; either version 2 or (at your option) any later version.
193
//
194
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
195
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
196
// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
197
// for more details.
198
//
199
// You should have received a copy of the GNU General Public License along
200
// with eCos; if not, write to the Free Software Foundation, Inc.,
201
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
202
//
203
// As a special exception, if other files instantiate templates or use macros
204
// or inline functions from this file, or you compile this file and link it
205
// with other works to produce a work based on this file, this file does not
206
// by itself cause the resulting work to be covered by the GNU General Public
207
// License. However the source code for this file must still be made available
208
// in accordance with section (3) of the GNU General Public License.
209
//
210
// This exception does not invalidate any other reasons why a work based on
211
// this file might be covered by the GNU General Public License.
212
//
213
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
214
// at http://sources.redhat.com/ecos/ecos-license/
215
// -------------------------------------------
216
//####ECOSGPLCOPYRIGHTEND####
217
//===========================================================================

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.