OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [rtos/] [ecos-2.0/] [packages/] [hal/] [arm/] [sa11x0/] [nano/] [v2_0/] [include/] [hal_platform_setup.h] - Blame information for rev 174

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 27 unneback
#ifndef CYGONCE_HAL_PLATFORM_SETUP_H
2
#define CYGONCE_HAL_PLATFORM_SETUP_H
3
 
4
/*=============================================================================
5
//
6
//      hal_platform_setup.h
7
//
8
//      Platform specific support for HAL (assembly code)
9
//
10
//=============================================================================
11
//####ECOSGPLCOPYRIGHTBEGIN####
12
// -------------------------------------------
13
// This file is part of eCos, the Embedded Configurable Operating System.
14
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
15
//
16
// eCos is free software; you can redistribute it and/or modify it under
17
// the terms of the GNU General Public License as published by the Free
18
// Software Foundation; either version 2 or (at your option) any later version.
19
//
20
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
21
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
22
// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
23
// for more details.
24
//
25
// You should have received a copy of the GNU General Public License along
26
// with eCos; if not, write to the Free Software Foundation, Inc.,
27
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
28
//
29
// As a special exception, if other files instantiate templates or use macros
30
// or inline functions from this file, or you compile this file and link it
31
// with other works to produce a work based on this file, this file does not
32
// by itself cause the resulting work to be covered by the GNU General Public
33
// License. However the source code for this file must still be made available
34
// in accordance with section (3) of the GNU General Public License.
35
//
36
// This exception does not invalidate any other reasons why a work based on
37
// this file might be covered by the GNU General Public License.
38
//
39
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
40
// at http://sources.redhat.com/ecos/ecos-license/
41
// -------------------------------------------
42
//####ECOSGPLCOPYRIGHTEND####
43
//=============================================================================
44
//#####DESCRIPTIONBEGIN####
45
//
46
// Author(s):    gthomas
47
// Contributors: hmt
48
// Date:         2001-02-12
49
// Purpose:      Intel SA1110/NanoEngine platform specific support routines
50
// Description:
51
// Usage:        #include <cyg/hal/hal_platform_setup.h>
52
//     Only used by "vectors.S"
53
//
54
//####DESCRIPTIONEND####
55
//
56
//===========================================================================*/
57
 
58
#include <pkgconf/system.h>             // System-wide configuration info
59
#include CYGBLD_HAL_VARIANT_H           // Variant (SA11x0) specific configuration
60
#include CYGBLD_HAL_PLATFORM_H          // Platform specific configuration
61
#include <cyg/hal/hal_sa11x0.h>         // Variant specific hardware definitions
62
#include <cyg/hal/hal_mmu.h>            // MMU definitions
63
#include <cyg/hal/nano.h>               // Platform specific hardware definitions
64
 
65
#if defined(CYG_HAL_STARTUP_ROM)
66
#define PLATFORM_SETUP1 _platform_setup1
67
#define CYGHWR_HAL_ARM_HAS_MMU
68
// Tell the architectural HAL we might not be at the base of FLASH:
69
#define CYGHWR_HAL_ROM_VADDR 0x50000000
70
 
71
#if (CYGHWR_HAL_ARM_SA11X0_PROCESSOR_CLOCK == 59000)
72
#define SA11X0_PLL_CLOCK 0x0        
73
#elif (CYGHWR_HAL_ARM_SA11X0_PROCESSOR_CLOCK == 73700)
74
#define SA11X0_PLL_CLOCK 0x1
75
#elif (CYGHWR_HAL_ARM_SA11X0_PROCESSOR_CLOCK == 88500)
76
#define SA11X0_PLL_CLOCK 0x2        
77
#elif (CYGHWR_HAL_ARM_SA11X0_PROCESSOR_CLOCK == 103200) 
78
#define SA11X0_PLL_CLOCK 0x3        
79
#elif (CYGHWR_HAL_ARM_SA11X0_PROCESSOR_CLOCK == 118000)
80
#define SA11X0_PLL_CLOCK 0x4        
81
#elif (CYGHWR_HAL_ARM_SA11X0_PROCESSOR_CLOCK == 132700)
82
#define SA11X0_PLL_CLOCK 0x5        
83
#elif (CYGHWR_HAL_ARM_SA11X0_PROCESSOR_CLOCK == 147500)
84
#define SA11X0_PLL_CLOCK 0x6        
85
#elif (CYGHWR_HAL_ARM_SA11X0_PROCESSOR_CLOCK == 162200)
86
#define SA11X0_PLL_CLOCK 0x7        
87
#elif (CYGHWR_HAL_ARM_SA11X0_PROCESSOR_CLOCK == 176900)
88
#define SA11X0_PLL_CLOCK 0x8        
89
#elif (CYGHWR_HAL_ARM_SA11X0_PROCESSOR_CLOCK == 191700)
90
#define SA11X0_PLL_CLOCK 0x9        
91
#elif (CYGHWR_HAL_ARM_SA11X0_PROCESSOR_CLOCK == 206400)
92
#define SA11X0_PLL_CLOCK 0xA        
93
#elif (CYGHWR_HAL_ARM_SA11X0_PROCESSOR_CLOCK == 221200)
94
#define SA11X0_PLL_CLOCK 0xB        
95
#else
96
#error Invalid processor clock speed
97
#endif                
98
 
99
// ------------------------------------------------------------------------
100
// These macros are in lieu of any LEDs on the board; in ROM <=> POST
101
// startup on the nanoEngine, the serial out is initialized already, so you
102
// can just poke chars into it:
103
 
104
#if 0
105
 
106
#define CYGHWR_ASCII                            \
107
        and     r1,r1,#0xf;                     \
108
        cmps    r1,#10;                         \
109
        subge   r1,r1,#10;                      \
110
        addge   r1,r1,#65;                      \
111
        addlt   r1,r1,#48;
112
 
113
#define CYGHWR_LED_MACRO                        \
114
        ldr     r0,=SA11X0_UART1_DATA;          \
115
        mov     r1,#255&((\x));                 \
116
        mov     r1,r1, lsr #4;                  \
117
        CYGHWR_ASCII                            \
118
        str     r1,[r0];                        \
119
        mov     r1,#255&((\x));                 \
120
        CYGHWR_ASCII                            \
121
        str     r1,[r0];                        \
122
        mov     r1,#0x2A;                       \
123
        str     r1,[r0];                        \
124
        PAUSE
125
 
126
#define PAUSE                                   \
127
        ldr     r1,=0x8000;                     \
128
555:    sub     r1,r1,#1;                       \
129
        cmp     r1,#0;                          \
130
        bne     555b;
131
 
132
#define OUT                                     \
133
        mov r2,r0;                              \
134
        mov r3,#8;                              \
135
        ldr r0,=SA11X0_UART1_DATA;              \
136
        mov r1,#'=';                            \
137
        str r1,[r0];                            \
138
        PAUSE                                   \
139
444:    mov r1,r2,lsr#28;                       \
140
        CYGHWR_ASCII                            \
141
        str r1,[r0];                            \
142
        mov r2,r2,asl#4;                        \
143
        subs r3,r3,#1;                          \
144
        bge 444b;                               \
145
        PAUSE                                   \
146
        mov r1,#' ';                            \
147
        str r1,[r0];                            \
148
        PAUSE                                   \
149
 
150
#endif // 0, to define CYGHWR_LED_MACRO et al
151
 
152
 
153
// ------------------------------------------------------------------------
154
// This macro represents the initial startup code for the platform        
155
        .macro  _platform_setup1
156
 
157
        // Turn off diagnostic LEDs
158
        LED 0x00
159
 
160
#ifdef CYGBLD_HAL_STARTUP_ROM_POST_BEFORE_ECOS
161
        // Then we must disable caches before starting initialization, else
162
        // the jump to hyperspace, um, high addresses after MM is enabled
163
        // will fail:
164
        ldr     r1,=MMU_Control_Init
165
        mcr     p15,0,r1,c1,c0
166
        // and flush/trash all caches and their TLBs:
167
        mov     r0,#0
168
        mcr     p15,0,r0,c7,c5,0 // Icache
169
        mcr     p15,0,r0,c8,c5,0 // ITLB
170
        mcr     p15,0,r0,c7,c6,0 // Dcache
171
        mcr     p15,0,r0,c8,c6,0 // DTLB
172
        // at least a linesworth of nops.
173
        nop
174
        nop
175
        nop
176
        nop
177
        nop
178
        nop
179
        nop
180
        nop
181
#endif
182
 
183
        LED     0x01
184
 
185
        // Set up GPIO - they're all inputs initially.
186
        ldr     r0,=SA1110_GPIO_GRER_DEFAULT_VALUE
187
        ldr     r1,=SA11X0_GPIO_RISING_EDGE_DETECT
188
        str     r0,[r1]
189
 
190
        ldr     r0,=SA1110_GPIO_GFER_DEFAULT_VALUE
191
        ldr     r1,=SA11X0_GPIO_FALLING_EDGE_DETECT
192
        str     r0,[r1]
193
 
194
        ldr     r0,=SA1110_GPIO_GPOSR_DEFAULT_VALUE
195
        ldr     r1,=SA11X0_GPIO_PIN_OUTPUT_SET
196
        str     r0,[r1]
197
 
198
        ldr     r0,=SA1110_GPIO_GPOCR_DEFAULT_VALUE
199
        ldr     r1,=SA11X0_GPIO_PIN_OUTPUT_CLEAR
200
        str     r0,[r1]
201
 
202
        ldr     r0,=SA1110_GPIO_GAFR_DEFAULT_VALUE
203
        ldr     r1,=SA11X0_GPIO_ALTERNATE_FUNCTION
204
        str     r0,[r1]
205
 
206
        // The other 3 leds should extinguish at this point
207
        ldr     r0,=SA1110_GPIO_GPDR_DEFAULT_VALUE
208
        ldr     r1,=SA11X0_GPIO_PIN_DIRECTION
209
        str     r0,[r1]
210
 
211
        LED     0x10
212
 
213
        // Disable clock switching
214
        mcr     p15,0,r0,\
215
                SA11X0_TEST_CLOCK_AND_IDLE_REGISTER,\
216
                SA11X0_DISABLE_CLOCK_SWITCHING_RM,\
217
                SA11X0_DISABLE_CLOCK_SWITCHING_OPCODE
218
 
219
        // Set up processor clock
220
        ldr     r1,=SA11X0_PWR_MGR_PLL_CONFIG
221
        ldr     r2,=SA11X0_PLL_CLOCK
222
        str     r2,[r1]
223
 
224
        // Turn clock switching back on
225
        mcr     p15,0,r0,\
226
                SA11X0_TEST_CLOCK_AND_IDLE_REGISTER,\
227
                SA11X0_ENABLE_CLOCK_SWITCHING_RM,\
228
                SA11X0_ENABLE_CLOCK_SWITCHING_OPCODE
229
        nop
230
        nop
231
 
232
        LED     0x40
233
 
234
#ifdef CYGBLD_HAL_STARTUP_ROM_POST_OMIT_SDRAM_INIT
235
        // If DRAM already enabled then skip its configuration.
236
        ldr     r1,=SA11X0_DRAM_CONFIGURATION
237
        ldr     r2,[r1]
238
        ands    r2, r2, #0xf
239
        bne     20f
240
#endif // CYGBLD_HAL_STARTUP_ROM_POST_OMIT_SDRAM_INIT
241
 
242
        // Initialize DRAM controller
243
        ldr     r1,=dram_table
244
        ldr     r2,=__exception_handlers
245
        sub     r1,r1,r2
246
        ldr     r2,[r1],#4                      // First control register
247
10:     ldr     r3,[r1],#4
248
        str     r3,[r2]
249
        ldr     r2,[r1],#4                      // Next control register
250
        cmp     r2,#0
251
        bne     10b
252
 
253
        LED 0x70
254
 
255
        // Release DRAM hold (set by RESET)
256
        ldr     r1,=SA11X0_PWR_MGR_SLEEP_STATUS
257
        ldr     r2,=SA11X0_DRAM_CONTROL_HOLD
258
        str     r2,[r1]
259
 
260
        LED     0x80
261
 
262
        // Perform 8 reads from unmapped/unenabled DRAM
263
        ldr     r1,=SA11X0_RAM_BANK0_BASE
264
        ldr     r2,[r1]
265
        ldr     r2,[r1]
266
        ldr     r2,[r1]
267
        ldr     r2,[r1]
268
        ldr     r2,[r1]
269
        ldr     r2,[r1]
270
        ldr     r2,[r1]
271
        ldr     r2,[r1]
272
 
273
        // Enable DRAM controller
274
        ldr     r1,=SA11X0_DRAM_CONFIGURATION
275
        ldr     r2,=0x00007255 // read from nanoEngine
276
        str     r2,[r1]
277
 
278
        b       19f
279
 
280
// DRAM controller initialization        
281
dram_table:
282
        // Data extracted from the setup of the nanoEngine
283
        .word   SA11X0_DRAM0_CAS_0,           0xAAAAAA7F
284
        .word   SA11X0_DRAM0_CAS_1,           0xAAAAAAAA
285
        .word   SA11X0_DRAM0_CAS_2,           0xAAAAAAAA
286
        .word   SA11X0_STATIC_CONTROL_0,      0xfff9fffc
287
        .word   SA11X0_STATIC_CONTROL_1,      0xfff9fff9
288
        .word   SA11X0_EXP_BUS_CONFIGURATION, 0x00000000
289
        .word   SA11X0_REFRESH_CONFIGURATION, 0x303401f5
290
        .word   SA11X0_DRAM2_CAS_0,           0xAAAAAA7F // uninitialized, 
291
        .word   SA11X0_DRAM2_CAS_1,           0xAAAAAAAA //    apparently
292
        .word   SA11X0_DRAM2_CAS_2,           0xAAAAAAAA //    these 3
293
        .word   SA11X0_STATIC_CONTROL_2,      0xfffcfff8
294
        .word   SA11X0_SMROM_CONFIGURATION,   0xf070c040
295
        .word   SA11X0_DRAM_CONFIGURATION,    0x72547254        // Disabled
296
        .word   0, 0
297
19:
298
 
299
        // Release peripheral hold (set by RESET)
300
        ldr     r1,=SA11X0_PWR_MGR_SLEEP_STATUS
301
        ldr     r2,=SA11X0_PERIPHERAL_CONTROL_HOLD
302
        str     r2,[r1]
303
 
304
20:
305
        LED     0x90
306
 
307
        // Enable UART
308
        ldr     r1,=SA1110_GPCLK_CONTROL_0
309
        ldr     r2,=SA1110_GPCLK_SUS_UART
310
        str     r2,[r1]
311
 
312
        LED     0xA0
313
 
314
        // Set up a stack [for calling C code]
315
        ldr     r1,=__startup_stack
316
        ldr     r2,=SA11X0_RAM_BANK0_BASE
317
        orr     sp,r1,r2
318
 
319
        LED     0xC0
320
 
321
        // Create MMU tables
322
        bl      hal_mmu_init
323
 
324
#if 0        
325
        LED     0xC1
326
        mrc     p15,0,r0,c1,c0,0
327
        OUT
328
        LED     0xC2
329
        mrc     p15,0,r0,c2,c0,0
330
        OUT
331
        LED     0xC3
332
        mrc     p15,0,r0,c3,c0,0
333
        OUT
334
        LED     0xCC
335
        mov     r0,pc
336
        OUT
337
#endif
338
 
339
        LED     0xE0
340
 
341
        // Enable MMU
342
        ldr     r2,=10f
343
        ldr     r1,=MMU_Control_Init|MMU_Control_M
344
        mcr     p15,0,r1,c1,c0
345
        mov     pc,r2    /* Change address spaces */
346
        nop
347
        nop
348
        nop
349
10:
350
 
351
        LED     0xF0
352
 
353
        .endm
354
 
355
#else // defined(CYG_HAL_STARTUP_ROM)
356
#define PLATFORM_SETUP1
357
#endif
358
 
359
#define PLATFORM_VECTORS         _platform_vectors
360
        .macro  _platform_vectors
361
        .endm
362
 
363
/*---------------------------------------------------------------------------*/
364
/* end of hal_platform_setup.h                                               */
365
#endif /* CYGONCE_HAL_PLATFORM_SETUP_H */

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.