| 1 |
27 |
unneback |
#ifndef CYGONCE_HAL_ARM_SA11X0_NANOENGINE_NANOENGINE_H
|
| 2 |
|
|
#define CYGONCE_HAL_ARM_SA11X0_NANOENGINE_NANOENGINE_H
|
| 3 |
|
|
|
| 4 |
|
|
/*=============================================================================
|
| 5 |
|
|
//
|
| 6 |
|
|
// nano.h
|
| 7 |
|
|
//
|
| 8 |
|
|
// Platform specific support (register layout, etc)
|
| 9 |
|
|
//
|
| 10 |
|
|
//=============================================================================
|
| 11 |
|
|
//####ECOSGPLCOPYRIGHTBEGIN####
|
| 12 |
|
|
// -------------------------------------------
|
| 13 |
|
|
// This file is part of eCos, the Embedded Configurable Operating System.
|
| 14 |
|
|
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
|
| 15 |
|
|
//
|
| 16 |
|
|
// eCos is free software; you can redistribute it and/or modify it under
|
| 17 |
|
|
// the terms of the GNU General Public License as published by the Free
|
| 18 |
|
|
// Software Foundation; either version 2 or (at your option) any later version.
|
| 19 |
|
|
//
|
| 20 |
|
|
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
|
| 21 |
|
|
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
| 22 |
|
|
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
|
| 23 |
|
|
// for more details.
|
| 24 |
|
|
//
|
| 25 |
|
|
// You should have received a copy of the GNU General Public License along
|
| 26 |
|
|
// with eCos; if not, write to the Free Software Foundation, Inc.,
|
| 27 |
|
|
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
|
| 28 |
|
|
//
|
| 29 |
|
|
// As a special exception, if other files instantiate templates or use macros
|
| 30 |
|
|
// or inline functions from this file, or you compile this file and link it
|
| 31 |
|
|
// with other works to produce a work based on this file, this file does not
|
| 32 |
|
|
// by itself cause the resulting work to be covered by the GNU General Public
|
| 33 |
|
|
// License. However the source code for this file must still be made available
|
| 34 |
|
|
// in accordance with section (3) of the GNU General Public License.
|
| 35 |
|
|
//
|
| 36 |
|
|
// This exception does not invalidate any other reasons why a work based on
|
| 37 |
|
|
// this file might be covered by the GNU General Public License.
|
| 38 |
|
|
//
|
| 39 |
|
|
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
|
| 40 |
|
|
// at http://sources.redhat.com/ecos/ecos-license/
|
| 41 |
|
|
// -------------------------------------------
|
| 42 |
|
|
//####ECOSGPLCOPYRIGHTEND####
|
| 43 |
|
|
//=============================================================================
|
| 44 |
|
|
//#####DESCRIPTIONBEGIN####
|
| 45 |
|
|
//
|
| 46 |
|
|
// Author(s): gthomas
|
| 47 |
|
|
// Contributors: gthomas,hmt
|
| 48 |
|
|
// Date: 2001-02-12
|
| 49 |
|
|
// Purpose: Intel SA1110/NanoEngine platform specific support routines
|
| 50 |
|
|
// Description:
|
| 51 |
|
|
// Usage: #include <cyg/hal/nano.h>
|
| 52 |
|
|
//
|
| 53 |
|
|
//####DESCRIPTIONEND####
|
| 54 |
|
|
//
|
| 55 |
|
|
//===========================================================================*/
|
| 56 |
|
|
|
| 57 |
|
|
#include <pkgconf/system.h>
|
| 58 |
|
|
#include CYGHWR_MEMORY_LAYOUT_H
|
| 59 |
|
|
|
| 60 |
|
|
#include <cyg/hal/hal_sa11x0.h>
|
| 61 |
|
|
|
| 62 |
|
|
//
|
| 63 |
|
|
// Signal assertion levels
|
| 64 |
|
|
//
|
| 65 |
|
|
#define SA1110_LOGIC_ONE(m) (m & 0xFFFFFFFF)
|
| 66 |
|
|
#define SA1110_LOGIC_ZERO(m) (m & 0x00000000)
|
| 67 |
|
|
|
| 68 |
|
|
//
|
| 69 |
|
|
// SA1110/NanoEngine Control Status registers
|
| 70 |
|
|
//
|
| 71 |
|
|
|
| 72 |
|
|
//
|
| 73 |
|
|
// Special purpose GPIO interrupt mappings
|
| 74 |
|
|
//
|
| 75 |
|
|
|
| 76 |
|
|
//
|
| 77 |
|
|
// GPIO layout
|
| 78 |
|
|
//
|
| 79 |
|
|
// 0-19 unused
|
| 80 |
|
|
// 20-27 unused
|
| 81 |
|
|
// 28-31 not implemented
|
| 82 |
|
|
//
|
| 83 |
|
|
// BUT PCI action can make use of GPIO 21 and 22 - but that's all set up in
|
| 84 |
|
|
// HAL_PCI_INIT() below, as it should be.
|
| 85 |
|
|
|
| 86 |
|
|
#define SA1110_GPIO_GPDR_DEFAULT_VALUE 0 // No GPIO is used
|
| 87 |
|
|
|
| 88 |
|
|
#define SA1110_GPIO_GAFR_DEFAULT_VALUE 0 // No alternates
|
| 89 |
|
|
|
| 90 |
|
|
#define SA1110_GPIO_GRER_DEFAULT_VALUE 0 // No edge detection at all
|
| 91 |
|
|
#define SA1110_GPIO_GFER_DEFAULT_VALUE 0 // No edge detection at all
|
| 92 |
|
|
|
| 93 |
|
|
#define SA1110_GPIO_GPOSR_DEFAULT_VALUE 0xffffffff // Set all 1s
|
| 94 |
|
|
#define SA1110_GPIO_GPOCR_DEFAULT_VALUE 0x00000000 // and leave them set
|
| 95 |
|
|
|
| 96 |
|
|
// ------------------------------------------------------------------------
|
| 97 |
|
|
//
|
| 98 |
|
|
// Interrupt numbers
|
| 99 |
|
|
//
|
| 100 |
|
|
#define SA1110_GPIO_INTR_ETH0 0 // CYGNUM_HAL_INTERRUPT_GPIO0
|
| 101 |
|
|
#define SA1110_GPIO_INTR_ETH1 1 // CYGNUM_HAL_INTERRUPT_GPIO1
|
| 102 |
|
|
|
| 103 |
|
|
// ------------------------------------------------------------------------
|
| 104 |
|
|
//
|
| 105 |
|
|
// PCI stuff
|
| 106 |
|
|
|
| 107 |
|
|
#ifndef __ASSEMBLER__
|
| 108 |
|
|
#ifdef CYGPKG_IO_PCI
|
| 109 |
|
|
|
| 110 |
|
|
#define CYGHWR_HAL_ARM_NANO_PCI_MEM_MAP_BASE ((cyg_uint32)(&CYGMEM_SECTION_pci_window[0]))
|
| 111 |
|
|
#define CYGHWR_HAL_ARM_NANO_PCI_MEM_MAP_SIZE ((cyg_uint32)(CYGMEM_SECTION_pci_window_SIZE))
|
| 112 |
|
|
|
| 113 |
|
|
extern cyg_uint32 cyg_pci_window_real_base;
|
| 114 |
|
|
|
| 115 |
|
|
#define HAL_PCI_INIT() CYG_MACRO_START \
|
| 116 |
|
|
cyg_uint32 t; \
|
| 117 |
|
|
/* Set up the DRAM system so that an alternate master can take control. */ \
|
| 118 |
|
|
/* This is described in section 10.8 pp10-67..68 of the SA1110 book. */ \
|
| 119 |
|
|
/* This is how the nanoBridge allows the 82559 ethernet devices to */ \
|
| 120 |
|
|
/* access main memory. Apparently. So much for documentation. */ \
|
| 121 |
|
|
\
|
| 122 |
|
|
/* Set GPIO pin direction: 21 out, 22 in. */ \
|
| 123 |
|
|
t = *SA11X0_GPIO_PIN_DIRECTION; \
|
| 124 |
|
|
t |= SA11X0_GPIO_PIN_21; \
|
| 125 |
|
|
t &=~SA11X0_GPIO_PIN_22; \
|
| 126 |
|
|
*SA11X0_GPIO_PIN_DIRECTION = t; \
|
| 127 |
|
|
\
|
| 128 |
|
|
/* Set alternate functions for GPIO 21 and 22. */ \
|
| 129 |
|
|
t = *SA11X0_GPIO_ALTERNATE_FUNCTION; \
|
| 130 |
|
|
t |= SA11X0_GPIO_PIN_21 + SA11X0_GPIO_PIN_22; \
|
| 131 |
|
|
*SA11X0_GPIO_ALTERNATE_FUNCTION = t; \
|
| 132 |
|
|
\
|
| 133 |
|
|
/* Set the Test Unit Control Register to enable external memory mastery */ \
|
| 134 |
|
|
t = *SA11X0_TUCR; \
|
| 135 |
|
|
t &=~SA11X0_TUCR_RESERVED_BITS; \
|
| 136 |
|
|
t |= SA11X0_TUCR_EXTERNAL_MEMORY_MASTER; \
|
| 137 |
|
|
*SA11X0_TUCR = t; \
|
| 138 |
|
|
\
|
| 139 |
|
|
/* Set the interrupts on GPIO0 and GPIO1 to be falling-edge */ \
|
| 140 |
|
|
\
|
| 141 |
|
|
/* GPIO0 and GPIO1 be inputs: */ \
|
| 142 |
|
|
t = *SA11X0_GPIO_PIN_DIRECTION; \
|
| 143 |
|
|
t &=~(SA11X0_GPIO_PIN_0 + SA11X0_GPIO_PIN_1); \
|
| 144 |
|
|
*SA11X0_GPIO_PIN_DIRECTION = t; \
|
| 145 |
|
|
/* no rising edge */ \
|
| 146 |
|
|
t = *SA11X0_GPIO_RISING_EDGE_DETECT; \
|
| 147 |
|
|
t &=~(SA11X0_GPIO_PIN_0 + SA11X0_GPIO_PIN_1); \
|
| 148 |
|
|
*SA11X0_GPIO_RISING_EDGE_DETECT = t; \
|
| 149 |
|
|
/* falling edge on */ \
|
| 150 |
|
|
t = *SA11X0_GPIO_FALLING_EDGE_DETECT; \
|
| 151 |
|
|
t |= (SA11X0_GPIO_PIN_0 + SA11X0_GPIO_PIN_1); \
|
| 152 |
|
|
*SA11X0_GPIO_FALLING_EDGE_DETECT = t; \
|
| 153 |
|
|
/* cancel any pending edges */ \
|
| 154 |
|
|
t = (SA11X0_GPIO_PIN_0 + SA11X0_GPIO_PIN_1); \
|
| 155 |
|
|
*SA11X0_GPIO_EDGE_DETECT_STATUS = t; \
|
| 156 |
|
|
\
|
| 157 |
|
|
/* and disconnect ethernet devices from the PCI bus so that they */ \
|
| 158 |
|
|
/* respond to being scanned a second time - because RedBoot will */ \
|
| 159 |
|
|
/* likely have enabled one or both of them already. */ \
|
| 160 |
|
|
/* We know that the two ethers are device #1 and #2: */ \
|
| 161 |
|
|
t = 0; \
|
| 162 |
|
|
HAL_PCI_CFG_WRITE_UINT16( 0, CYG_PCI_DEV_MAKE_DEVFN(1,0), \
|
| 163 |
|
|
CYG_PCI_CFG_COMMAND, t ); \
|
| 164 |
|
|
t = 0; \
|
| 165 |
|
|
HAL_PCI_CFG_WRITE_UINT16( 0, CYG_PCI_DEV_MAKE_DEVFN(2,0), \
|
| 166 |
|
|
CYG_PCI_CFG_COMMAND, t ); \
|
| 167 |
|
|
CYG_MACRO_END
|
| 168 |
|
|
|
| 169 |
|
|
// This is nasty in the nanoBridge; it does NOT correctly return -1's for
|
| 170 |
|
|
// empty config slots, it lies and gives the impression of there being lots
|
| 171 |
|
|
// of extra nothing devices. So we have to fake it.
|
| 172 |
|
|
|
| 173 |
|
|
// Compute address necessary to access PCI config space for the given bus
|
| 174 |
|
|
// and device. With faked gaps...
|
| 175 |
|
|
#define HAL_PCI_CONFIG_ADDRESS( __bus, __devfn, __offset ) \
|
| 176 |
|
|
({ \
|
| 177 |
|
|
cyg_uint32 __addr; \
|
| 178 |
|
|
cyg_uint32 __dev = CYG_PCI_DEV_GET_DEV(__devfn); \
|
| 179 |
|
|
__addr = (0 == __bus) ? 0x18A00000 : 0xffffffffu; \
|
| 180 |
|
|
__addr |= (1 == __dev || 2 == __dev) ? (__dev << 16) : 0xffffffffu; \
|
| 181 |
|
|
__addr |= CYG_PCI_DEV_GET_FN(__devfn) << 8; \
|
| 182 |
|
|
__addr |= __offset; \
|
| 183 |
|
|
__addr; \
|
| 184 |
|
|
})
|
| 185 |
|
|
|
| 186 |
|
|
// Not used. For experiments, or for a more general PCI bus...
|
| 187 |
|
|
#define scan_all_HAL_PCI_CONFIG_ADDRESS( __bus, __devfn, __offset ) \
|
| 188 |
|
|
({ \
|
| 189 |
|
|
cyg_uint32 __addr; \
|
| 190 |
|
|
cyg_uint32 __dev = CYG_PCI_DEV_GET_DEV(__devfn); \
|
| 191 |
|
|
__addr = (0 == __bus) ? 0x18A00000 : 0xffffffffu; \
|
| 192 |
|
|
__addr |= __dev << 16; \
|
| 193 |
|
|
__addr |= CYG_PCI_DEV_GET_FN(__devfn) << 8; \
|
| 194 |
|
|
__addr |= __offset; \
|
| 195 |
|
|
__addr; \
|
| 196 |
|
|
})
|
| 197 |
|
|
|
| 198 |
|
|
#define HAL_PCI_DO_CONFIG_ACCESS( __bus, __devfn, __offset, __val, __action, __type ) \
|
| 199 |
|
|
{ \
|
| 200 |
|
|
cyg_uint32 __doaddr = HAL_PCI_CONFIG_ADDRESS( __bus, __devfn, __offset ); \
|
| 201 |
|
|
if ( 0xffffffffu == __doaddr ) \
|
| 202 |
|
|
__val = (__type)0xffffffffu; \
|
| 203 |
|
|
else { \
|
| 204 |
|
|
__action( __doaddr, __val ); \
|
| 205 |
|
|
/* nasty kludge to detect the absence of a second eth device on nanoEngines \
|
| 206 |
|
|
* rather than commEngines. The vendor should never be 0 or 256. */ \
|
| 207 |
|
|
if ( (__offset) == CYG_PCI_CFG_VENDOR && ((__val) == 0 || (__val) == 256) ) \
|
| 208 |
|
|
__val = (__type)0xffffffffu; \
|
| 209 |
|
|
} \
|
| 210 |
|
|
}
|
| 211 |
|
|
|
| 212 |
|
|
// Read/write a value from the PCI configuration space of the appropriate
|
| 213 |
|
|
// size at an address composed from the bus, devfn and offset.
|
| 214 |
|
|
#define HAL_PCI_CFG_READ_UINT8( __bus, __devfn, __offset, __val ) \
|
| 215 |
|
|
HAL_PCI_DO_CONFIG_ACCESS( __bus, __devfn, __offset, __val, HAL_READ_UINT8 , cyg_uint8 )
|
| 216 |
|
|
#define HAL_PCI_CFG_READ_UINT16( __bus, __devfn, __offset, __val ) \
|
| 217 |
|
|
HAL_PCI_DO_CONFIG_ACCESS( __bus, __devfn, __offset, __val, HAL_READ_UINT16 , cyg_uint16 )
|
| 218 |
|
|
#define HAL_PCI_CFG_READ_UINT32( __bus, __devfn, __offset, __val ) \
|
| 219 |
|
|
HAL_PCI_DO_CONFIG_ACCESS( __bus, __devfn, __offset, __val, HAL_READ_UINT32 , cyg_uint32 )
|
| 220 |
|
|
#define HAL_PCI_CFG_WRITE_UINT8( __bus, __devfn, __offset, __val ) \
|
| 221 |
|
|
HAL_PCI_DO_CONFIG_ACCESS( __bus, __devfn, __offset, __val, HAL_WRITE_UINT8 , cyg_uint8 )
|
| 222 |
|
|
#define HAL_PCI_CFG_WRITE_UINT16( __bus, __devfn, __offset, __val ) \
|
| 223 |
|
|
HAL_PCI_DO_CONFIG_ACCESS( __bus, __devfn, __offset, __val, HAL_WRITE_UINT16, cyg_uint16 )
|
| 224 |
|
|
#define HAL_PCI_CFG_WRITE_UINT32( __bus, __devfn, __offset, __val ) \
|
| 225 |
|
|
HAL_PCI_DO_CONFIG_ACCESS( __bus, __devfn, __offset, __val, HAL_WRITE_UINT32, cyg_uint32 )
|
| 226 |
|
|
|
| 227 |
|
|
//-----------------------------------------------------------------------------
|
| 228 |
|
|
// Resources
|
| 229 |
|
|
|
| 230 |
|
|
// Map PCI device resources starting from these addresses in PCI space.
|
| 231 |
|
|
#define HAL_PCI_ALLOC_BASE_MEMORY (0x00000000)
|
| 232 |
|
|
#define HAL_PCI_ALLOC_BASE_IO (0x00000000)
|
| 233 |
|
|
|
| 234 |
|
|
// This is where the PCI spaces are mapped in the CPU's address space.
|
| 235 |
|
|
#define HAL_PCI_PHYSICAL_MEMORY_BASE (0x18620000)
|
| 236 |
|
|
#define HAL_PCI_PHYSICAL_IO_BASE (0x18200000)
|
| 237 |
|
|
|
| 238 |
|
|
// Translate the PCI interrupt requested by the device (INTA#, INTB#,
|
| 239 |
|
|
// INTC# or INTD#) to the associated CPU interrupt (i.e., HAL vector).
|
| 240 |
|
|
#define HAL_PCI_TRANSLATE_INTERRUPT( __bus, __devfn, __vec, __valid) { \
|
| 241 |
|
|
cyg_uint32 __dev = CYG_PCI_DEV_GET_DEV(__devfn); \
|
| 242 |
|
|
__valid = false; \
|
| 243 |
|
|
if ( 1 == __dev || 2 == __dev ) { \
|
| 244 |
|
|
__vec = ( 1 == __dev ) ? SA1110_GPIO_INTR_ETH0 \
|
| 245 |
|
|
: SA1110_GPIO_INTR_ETH1; \
|
| 246 |
|
|
__valid = true; \
|
| 247 |
|
|
} \
|
| 248 |
|
|
}
|
| 249 |
|
|
|
| 250 |
|
|
|
| 251 |
|
|
#endif // CYGPKG_IO_PCI
|
| 252 |
|
|
#endif // #ifndef __ASSEMBLER__
|
| 253 |
|
|
// ------------------------------------------------------------------------
|
| 254 |
|
|
|
| 255 |
|
|
#endif // CYGONCE_HAL_ARM_SA11X0_NANOENGINE_NANOENGINE_H
|
| 256 |
|
|
// EOF nano.h
|
