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[/] [openrisc/] [trunk/] [rtos/] [ecos-2.0/] [packages/] [hal/] [arm/] [sa11x0/] [var/] [v2_0/] [include/] [hal_cache.h] - Blame information for rev 174

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#ifndef CYGONCE_HAL_CACHE_H
2
#define CYGONCE_HAL_CACHE_H
3
 
4
//=============================================================================
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//
6
//      hal_cache.h
7
//
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//      HAL cache control API
9
//
10
//=============================================================================
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//####ECOSGPLCOPYRIGHTBEGIN####
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// -------------------------------------------
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// This file is part of eCos, the Embedded Configurable Operating System.
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// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
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//
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// eCos is free software; you can redistribute it and/or modify it under
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// the terms of the GNU General Public License as published by the Free
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// Software Foundation; either version 2 or (at your option) any later version.
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//
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// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or
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// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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// for more details.
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//
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// You should have received a copy of the GNU General Public License along
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// with eCos; if not, write to the Free Software Foundation, Inc.,
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// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
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//
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// As a special exception, if other files instantiate templates or use macros
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// or inline functions from this file, or you compile this file and link it
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// with other works to produce a work based on this file, this file does not
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// by itself cause the resulting work to be covered by the GNU General Public
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// License. However the source code for this file must still be made available
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// in accordance with section (3) of the GNU General Public License.
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//
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// This exception does not invalidate any other reasons why a work based on
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// this file might be covered by the GNU General Public License.
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//
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// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
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// at http://sources.redhat.com/ecos/ecos-license/
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// -------------------------------------------
42
//####ECOSGPLCOPYRIGHTEND####
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//=============================================================================
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//#####DESCRIPTIONBEGIN####
45
//
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// Author(s):   gthomas
47
// Contributors:hmt
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//              Travis C. Furrer <furrer@mit.edu>
49
// Date:        2000-05-08
50
// Purpose:     Cache control API
51
// Description: The macros defined here provide the HAL APIs for handling
52
//              cache control operations.
53
// Usage:
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//              #include <cyg/hal/hal_cache.h>
55
//              ...
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//              
57
//
58
//####DESCRIPTIONEND####
59
//
60
//=============================================================================
61
 
62
#include <cyg/infra/cyg_type.h>
63
#include <cyg/hal/hal_sa11x0.h>
64
#include <cyg/hal/hal_mmu.h>
65
 
66
//-----------------------------------------------------------------------------
67
// FIXME: This definition forces the IO flash driver to use a
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// known-good procedure for fiddling flash before calling flash device
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// driver functions. The procedure breaks on other platform/driver
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// combinations though so is depricated. Hence this definition.
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//
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// If you work on this target, please try to remove this definition
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// and verify that the flash driver still works (both from RAM and
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// flash). If it does, remove the definition and this comment for good
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// [and the old macro definition if this happens to be the last client
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// of that code].
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#if defined(CYGPKG_HAL_ARM_SA11X0_ASSABET) \
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    || defined(CYGPKG_HAL_ARM_SA11X0_SA1100MM)
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# define HAL_FLASH_CACHES_OLD_MACROS
80
#endif
81
 
82
//-----------------------------------------------------------------------------
83
// Cache dimensions
84
 
85
#define HAL_ICACHE_SIZE                 SA11X0_ICACHE_SIZE
86
#define HAL_ICACHE_LINE_SIZE            SA11X0_ICACHE_LINESIZE_BYTES
87
#define HAL_ICACHE_WAYS                 SA11X0_ICACHE_WAYS
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#define HAL_ICACHE_SETS (HAL_ICACHE_SIZE/(HAL_ICACHE_LINE_SIZE*HAL_ICACHE_WAYS))
89
 
90
#define HAL_DCACHE_SIZE                 SA11X0_DCACHE_SIZE
91
#define HAL_DCACHE_LINE_SIZE            SA11X0_DCACHE_LINESIZE_BYTES
92
#define HAL_DCACHE_WAYS                 SA11X0_DCACHE_WAYS
93
#define HAL_DCACHE_SETS (HAL_DCACHE_SIZE/(HAL_DCACHE_LINE_SIZE*HAL_DCACHE_WAYS))
94
 
95
// FIXME: much of the code below should make better use of
96
// the definitions from hal_mmu.h
97
 
98
//-----------------------------------------------------------------------------
99
// Global control of Instruction cache
100
 
101
// Enable the instruction cache
102
#define HAL_ICACHE_ENABLE()                                             \
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CYG_MACRO_START                                                         \
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    asm volatile (                                                      \
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        "mrc  p15,0,r1,c1,c0,0;"                                        \
106
        "orr  r1,r1,#0x1000;"                                           \
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        "orr  r1,r1,#0x0003;" /* enable ICache (also ensures   */       \
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                              /* that MMU and alignment faults */       \
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                              /* are enabled)                  */       \
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        "mcr  p15,0,r1,c1,c0,0"                                         \
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        :                                                               \
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        :                                                               \
113
        : "r1" /* Clobber list */                                       \
114
        );                                                              \
115
CYG_MACRO_END
116
 
117
// Disable the instruction cache (and invalidate it, required semanitcs)
118
#define HAL_ICACHE_DISABLE()                                            \
119
CYG_MACRO_START                                                         \
120
    asm volatile (                                                      \
121
        "mrc    p15,0,r1,c1,c0,0;"                                      \
122
        "bic    r1,r1,#0x1000;" /* disable ICache (but not MMU, etc) */ \
123
        "mcr    p15,0,r1,c1,c0,0;"                                      \
124
        "mov    r1,#0;"                                                 \
125
        "mcr    p15,0,r1,c7,c5,0;"  /* flush ICache */                  \
126
        "nop;" /* next few instructions may be via cache    */          \
127
        "nop;"                                                          \
128
        "nop;"                                                          \
129
        "nop;"                                                          \
130
        "nop;"                                                          \
131
        "nop"                                                           \
132
        :                                                               \
133
        :                                                               \
134
        : "r1" /* Clobber list */                                       \
135
        );                                                              \
136
CYG_MACRO_END
137
 
138
// Query the state of the instruction cache
139
#define HAL_ICACHE_IS_ENABLED(_state_)                                   \
140
CYG_MACRO_START                                                          \
141
    register cyg_uint32 reg;                                             \
142
    asm volatile ("mrc  p15,0,%0,c1,c0,0"                                \
143
                  : "=r"(reg)                                            \
144
                  :                                                      \
145
        );                                                               \
146
    (_state_) = (0 != (0x1000 & reg)); /* Bit 12 is ICache enable */     \
147
CYG_MACRO_END
148
 
149
// Invalidate the entire cache
150
#define HAL_ICACHE_INVALIDATE_ALL()                                     \
151
CYG_MACRO_START                                                         \
152
    /* this macro can discard dirty cache lines (N/A for ICache) */     \
153
    asm volatile (                                                      \
154
        "mov    r1,#0;"                                                 \
155
        "mcr    p15,0,r1,c7,c5,0;"  /* flush ICache */                  \
156
        "mcr    p15,0,r1,c8,c5,0;"  /* flush ITLB only */               \
157
        "nop;" /* next few instructions may be via cache    */          \
158
        "nop;"                                                          \
159
        "nop;"                                                          \
160
        "nop;"                                                          \
161
        "nop;"                                                          \
162
        "nop;"                                                          \
163
        :                                                               \
164
        :                                                               \
165
        : "r1" /* Clobber list */                                       \
166
        );                                                              \
167
CYG_MACRO_END
168
 
169
// Synchronize the contents of the cache with memory.
170
// (which includes flushing out pending writes)
171
#define HAL_ICACHE_SYNC()                                       \
172
CYG_MACRO_START                                                 \
173
    HAL_DCACHE_SYNC(); /* ensure data gets to RAM */            \
174
    HAL_ICACHE_INVALIDATE_ALL(); /* forget all we know */       \
175
CYG_MACRO_END
176
 
177
// Set the instruction cache refill burst size
178
//#define HAL_ICACHE_BURST_SIZE(_size_)
179
// This feature is not available on the SA11X0.
180
 
181
// Load the contents of the given address range into the instruction cache
182
// and then lock the cache so that it stays there.
183
//#define HAL_ICACHE_LOCK(_base_, _size_)
184
// This feature is not available on the SA11X0.
185
 
186
// Undo a previous lock operation
187
//#define HAL_ICACHE_UNLOCK(_base_, _size_)
188
// This feature is not available on the SA11X0.
189
 
190
// Unlock entire cache
191
//#define HAL_ICACHE_UNLOCK_ALL()
192
// This feature is not available on the SA11X0.
193
 
194
//-----------------------------------------------------------------------------
195
// Instruction cache line control
196
 
197
// Invalidate cache lines in the given range without writing to memory.
198
//#define HAL_ICACHE_INVALIDATE( _base_ , _size_ )
199
// This feature is not available on the SA11X0.
200
 
201
//-----------------------------------------------------------------------------
202
// Global control of data cache
203
 
204
// Enable the data cache
205
#define HAL_DCACHE_ENABLE()                                             \
206
CYG_MACRO_START                                                         \
207
    asm volatile (                                                      \
208
        "mrc  p15,0,r1,c1,c0,0;"                                        \
209
        "orr  r1,r1,#0x000F;" /* enable DCache (also ensures    */      \
210
                              /* the MMU, alignment faults, and */      \
211
                              /* write buffer are enabled)      */      \
212
        "mcr  p15,0,r1,c1,c0,0"                                         \
213
        :                                                               \
214
        :                                                               \
215
        : "r1" /* Clobber list */                                       \
216
        );                                                              \
217
CYG_MACRO_END
218
 
219
// Disable the data cache (and invalidate it, required semanitcs)
220
#define HAL_DCACHE_DISABLE()                                            \
221
CYG_MACRO_START                                                         \
222
    asm volatile (                                                      \
223
        "mrc  p15,0,r1,c1,c0,0;"                                        \
224
        "bic  r1,r1,#0x000C;" /* disable DCache AND write buffer  */    \
225
                              /* but not MMU and alignment faults */    \
226
        "mcr  p15,0,r1,c1,c0,0;"                                        \
227
        "mov    r1,#0;"                                                 \
228
        "mcr  p15,0,r1,c7,c6,0" /* clear data cache */                  \
229
        :                                                               \
230
        :                                                               \
231
        : "r1" /* Clobber list */                                       \
232
        );                                                              \
233
CYG_MACRO_END
234
 
235
// Query the state of the data cache
236
#define HAL_DCACHE_IS_ENABLED(_state_)                                   \
237
CYG_MACRO_START                                                          \
238
    register int reg;                                                    \
239
    asm volatile ("mrc  p15,0,%0,c1,c0,0;"                               \
240
                  : "=r"(reg)                                            \
241
                  :                                                      \
242
        );                                                               \
243
    (_state_) = (0 != (4 & reg)); /* Bit 2 is DCache enable */           \
244
CYG_MACRO_END
245
 
246
// Flush the entire dcache (and then both TLBs, just in case)
247
#define HAL_DCACHE_INVALIDATE_ALL()                                     \
248
CYG_MACRO_START    /* this macro can discard dirty cache lines. */      \
249
    asm volatile (                                                      \
250
        "mov    r1,#0;"                                                 \
251
        "mcr    p15,0,r1,c7,c6,0;"                                      \
252
        "mcr    p15,0,r1,c8,c7,0;"                                      \
253
        :                                                               \
254
        :                                                               \
255
        : "r1","memory" );                                              \
256
CYG_MACRO_END
257
 
258
 
259
// Synchronize the contents of the cache with memory.
260
#define HAL_DCACHE_SYNC()                                               \
261
CYG_MACRO_START                                                         \
262
    /* This is slightly naff in that the only way to force a dirty */   \
263
    /* line out is by loading other data into its slot, so         */   \
264
    /* invalidating that slot.                                     */   \
265
    asm volatile (                                                      \
266
        "mov    r0, #0xE0000000;" /* SA11X0 zeros bank (128Mb) */       \
267
        "add    r1, r0, #0x2000;" /* We read 8kB of it */               \
268
 "667: "                                                                \
269
        "ldr    r2, [r0], #32;"                                         \
270
        "teq    r1, r0;"                                                \
271
        "bne    667b;"                                                  \
272
        "mov    r0,#0;"                                                 \
273
        "mcr    p15,0,r0,c7,c6,0;"  /* flush DCache */                  \
274
        "mcr    p15,0,r0,c7,c10,4;" /* and drain the write buffer */    \
275
        :                                                               \
276
        :                                                               \
277
        : "r0","r1","r2" /* Clobber list */                             \
278
        );                                                              \
279
CYG_MACRO_END
280
 
281
// Set the data cache refill burst size
282
//#define HAL_DCACHE_BURST_SIZE(_size_)
283
// This feature is not available on the SA11X0.
284
 
285
// Set the data cache write mode
286
//#define HAL_DCACHE_WRITE_MODE( _mode_ )
287
// This feature is not available on the SA11X0.
288
 
289
#define HAL_DCACHE_WRITETHRU_MODE       0
290
#define HAL_DCACHE_WRITEBACK_MODE       1
291
 
292
// Get the current writeback mode - or only writeback mode if fixed
293
#define HAL_DCACHE_QUERY_WRITE_MODE( _mode_ ) CYG_MACRO_START           \
294
    _mode_ = HAL_DCACHE_WRITEBACK_MODE;                                 \
295
CYG_MACRO_END
296
 
297
// Load the contents of the given address range into the data cache
298
// and then lock the cache so that it stays there.
299
//#define HAL_DCACHE_LOCK(_base_, _size_)
300
// This feature is not available on the SA11X0.
301
 
302
// Undo a previous lock operation
303
//#define HAL_DCACHE_UNLOCK(_base_, _size_)
304
// This feature is not available on the SA11X0.
305
 
306
// Unlock entire cache
307
//#define HAL_DCACHE_UNLOCK_ALL()
308
// This feature is not available on the SA11X0.
309
 
310
//-----------------------------------------------------------------------------
311
// Data cache line control
312
 
313
// Allocate cache lines for the given address range without reading its
314
// contents from memory.
315
//#define HAL_DCACHE_ALLOCATE( _base_ , _size_ )
316
// This feature is not available on the SA11X0.
317
 
318
// Write dirty cache lines to memory and invalidate the cache entries
319
// for the given address range.
320
#define HAL_DCACHE_FLUSH( _base_ , _size_ )     \
321
CYG_MACRO_START                                 \
322
    HAL_DCACHE_STORE( _base_ , _size_ );        \
323
    HAL_DCACHE_INVALIDATE( _base_ , _size_ );   \
324
CYG_MACRO_END
325
 
326
// Invalidate cache lines in the given range without writing to memory.
327
#define HAL_DCACHE_INVALIDATE( _base_ , _size_ )                        \
328
CYG_MACRO_START                                                         \
329
    register int addr, enda;                                            \
330
    for ( addr = (~(HAL_DCACHE_LINE_SIZE - 1)) & (int)(_base_),         \
331
              enda = (int)(_base_) + (_size_);                          \
332
          addr < enda ;                                                 \
333
          addr += HAL_DCACHE_LINE_SIZE )                                \
334
    {                                                                   \
335
        asm volatile (                                                  \
336
                      "mcr  p15,0,%0,c7,c6,1;" /* flush entry away */   \
337
                      :                                                 \
338
                      : "r"(addr)                                       \
339
                      : "memory"                                        \
340
            );                                                          \
341
    }                                                                   \
342
CYG_MACRO_END
343
 
344
// Write dirty cache lines to memory for the given address range.
345
#define HAL_DCACHE_STORE( _base_ , _size_ )                             \
346
CYG_MACRO_START                                                         \
347
    register int addr, enda;                                            \
348
    for ( addr = (~(HAL_DCACHE_LINE_SIZE - 1)) & (int)(_base_),         \
349
              enda = (int)(_base_) + (_size_);                          \
350
          addr < enda ;                                                 \
351
          addr += HAL_DCACHE_LINE_SIZE )                                \
352
    {                                                                   \
353
        asm volatile ("mcr  p15,0,%0,c7,c10,1;" /* push entry to RAM */ \
354
                      :                                                 \
355
                      : "r"(addr)                                       \
356
                      : "memory"                                        \
357
            );                                                          \
358
    }                                                                   \
359
    /* and also drain the write buffer */                               \
360
    asm volatile (                                                      \
361
        "mov    r1,#0;"                                                 \
362
        "mcr    p15,0,r1,c7,c10,4;"                                     \
363
        :                                                               \
364
        :                                                               \
365
        : "r1", "memory" /* Clobber list */                             \
366
    );                                                                  \
367
CYG_MACRO_END
368
 
369
// Preread the given range into the cache with the intention of reading
370
// from it later.
371
//#define HAL_DCACHE_READ_HINT( _base_ , _size_ )
372
// This feature is available on the SA11X0, but due to tricky
373
// coherency issues with the read buffer (see SA11X0 developer's
374
// manual page 6-7) we don't bother to implement it here.
375
 
376
// Preread the given range into the cache with the intention of writing
377
// to it later.
378
//#define HAL_DCACHE_WRITE_HINT( _base_ , _size_ )
379
// This feature is not available on the SA11X0.
380
 
381
// Allocate and zero the cache lines associated with the given range.
382
//#define HAL_DCACHE_ZERO( _base_ , _size_ )
383
// This feature is not available on the SA11X0.
384
 
385
//-----------------------------------------------------------------------------
386
// Now include the details of the platform's Memory Map setup:
387
 
388
#include <cyg/hal/plf_mmap.h>
389
 
390
// and define the (considerably less efficient) routines that are available
391
// for testing the actual memory map in force.
392
 
393
externC cyg_uint32 hal_virt_to_phys_address( cyg_uint32 vaddr );
394
externC cyg_uint32 hal_phys_to_virt_address( cyg_uint32 paddr );
395
externC cyg_uint32 hal_virt_to_uncached_address( cyg_uint32 vaddr );
396
 
397
//-----------------------------------------------------------------------------
398
#endif // ifndef CYGONCE_HAL_CACHE_H
399
// End of hal_cache.h

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