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#ifndef CYGONCE_HAL_CACHE_H
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#define CYGONCE_HAL_CACHE_H
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//=============================================================================
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//
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// hal_cache.h
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//
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// HAL cache control API
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//
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//=============================================================================
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//####ECOSGPLCOPYRIGHTBEGIN####
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// -------------------------------------------
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// This file is part of eCos, the Embedded Configurable Operating System.
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// Copyright (C) 1998, 1999, 2000, 2001, 2002, 2003 Red Hat, Inc.
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//
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// eCos is free software; you can redistribute it and/or modify it under
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// the terms of the GNU General Public License as published by the Free
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// Software Foundation; either version 2 or (at your option) any later version.
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//
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// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// for more details.
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//
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// You should have received a copy of the GNU General Public License along
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// with eCos; if not, write to the Free Software Foundation, Inc.,
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// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
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//
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// As a special exception, if other files instantiate templates or use macros
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// or inline functions from this file, or you compile this file and link it
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// with other works to produce a work based on this file, this file does not
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// by itself cause the resulting work to be covered by the GNU General Public
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// License. However the source code for this file must still be made available
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// in accordance with section (3) of the GNU General Public License.
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//
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// This exception does not invalidate any other reasons why a work based on
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// this file might be covered by the GNU General Public License.
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//
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// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
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// at http://sources.redhat.com/ecos/ecos-license/
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// -------------------------------------------
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//####ECOSGPLCOPYRIGHTEND####
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//=============================================================================
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//#####DESCRIPTIONBEGIN####
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//
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// Author(s): msalter
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// Contributors:
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// Date: 2001-12-03
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// Purpose: Cache control API
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// Description: The macros defined here provide the HAL APIs for handling
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// cache control operations.
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// Usage:
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// #include <cyg/hal/hal_cache.h>
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// ...
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//
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//
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//####DESCRIPTIONEND####
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//
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//=============================================================================
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#include <pkgconf/system.h> // System-wide configuration info
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#include <cyg/hal/hal_io.h> // DCACHE_FLUSH_AREA
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#include <cyg/infra/cyg_type.h>
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#include CYGBLD_HAL_VAR_H
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#include <cyg/hal/hal_mmu.h>
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//-----------------------------------------------------------------------------
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// Cache dimensions
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#define HAL_DCACHE_SIZE 0x8000 // Size of data cache in bytes
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#define HAL_DCACHE_LINE_SIZE 32 // Size of a data cache line
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#define HAL_DCACHE_WAYS 32 // Associativity of the cache
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#define HAL_DCACHE_SETS (HAL_DCACHE_SIZE/(HAL_DCACHE_LINE_SIZE*HAL_DCACHE_WAYS))
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#define HAL_ICACHE_SIZE 0x8000 // Size of icache in bytes
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#define HAL_ICACHE_LINE_SIZE 32 // Size of ins cache line
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#define HAL_ICACHE_WAYS 32 // Associativity of the cache
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#define HAL_ICACHE_SETS (HAL_ICACHE_SIZE/(HAL_ICACHE_LINE_SIZE*HAL_ICACHE_WAYS))
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//-----------------------------------------------------------------------------
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// Global control of Instruction cache
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// Enable the instruction cache
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#define HAL_ICACHE_ENABLE() \
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CYG_MACRO_START \
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asm volatile ( \
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"mrc p15,0,r1,c1,c0,0;" \
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"orr r1,r1,#0x1000;" /* enable ICache */ \
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"mcr p15,0,r1,c1,c0,0;" \
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: \
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: \
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: "r1" /* Clobber list */ \
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); \
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CYG_MACRO_END
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// Disable the instruction cache (and invalidate it, required semanitcs)
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#define HAL_ICACHE_DISABLE() \
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CYG_MACRO_START \
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asm volatile ( \
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"mrc p15,0,r1,c1,c0,0;" \
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"bic r1,r1,#0x1000;" /* disable Icache */ \
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"mcr p15,0,r1,c1,c0,0;" \
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"mcr p15,0,r1,c7,c5,0;" /* invalidate instruction cache */ \
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"nop;" /* next few instructions may be via cache */ \
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"nop;" \
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"nop;" \
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"nop;" \
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"nop;" \
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"nop" \
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: \
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: \
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: "r1" /* Clobber list */ \
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); \
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CYG_MACRO_END
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// Query the state of the instruction cache
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#define HAL_ICACHE_IS_ENABLED(_state_) \
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CYG_MACRO_START \
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register cyg_uint32 reg; \
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asm volatile ("mrc p15,0,%0,c1,c0,0" \
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: "=r"(reg) \
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: \
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); \
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(_state_) = (0 != (0x1000 & reg)); /* Bit 12 is ICache enable */ \
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CYG_MACRO_END
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// Invalidate the entire cache
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#define HAL_ICACHE_INVALIDATE_ALL() \
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CYG_MACRO_START \
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asm volatile ( \
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"mcr p15,0,r1,c7,c5,0;" /* clear instruction cache */ \
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"mcr p15,0,r1,c8,c5,0;" /* flush I TLB only */ \
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/* cpuwait */ \
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"mrc p15,0,r1,c2,c0,0;" /* arbitrary read */ \
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"mov r1,r1;" \
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"sub pc,pc,#4;" \
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"nop;" /* next few instructions may be via cache */ \
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"nop;" \
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"nop;" \
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"nop;" \
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"nop;" \
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"nop" \
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: \
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: \
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: "r1" /* Clobber list */ \
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); \
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CYG_MACRO_END
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// Synchronize the contents of the cache with memory.
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// (which includes flushing out pending writes)
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#define HAL_ICACHE_SYNC() \
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CYG_MACRO_START \
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HAL_DCACHE_SYNC(); /* ensure data gets to RAM */ \
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HAL_ICACHE_INVALIDATE_ALL(); /* forget all we know */ \
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CYG_MACRO_END
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// Set the instruction cache refill burst size
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//#define HAL_ICACHE_BURST_SIZE(_size_)
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// This feature is not available on the XScale.
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// Load the contents of the given address range into the instruction cache
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// and then lock the cache so that it stays there.
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//#define HAL_ICACHE_LOCK(_base_, _size_)
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// This feature is not available on the XScale.
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// Undo a previous lock operation
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//#define HAL_ICACHE_UNLOCK(_base_, _size_)
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// This feature is not available on the XScale.
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// Unlock entire cache
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//#define HAL_ICACHE_UNLOCK_ALL()
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// This feature is not available on the XScale.
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//-----------------------------------------------------------------------------
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// Instruction cache line control
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// Invalidate cache lines in the given range without writing to memory.
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//#define HAL_ICACHE_INVALIDATE( _base_ , _size_ )
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// This feature is not available on the XScale.
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//-----------------------------------------------------------------------------
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// Global control of data cache
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// Enable the data cache
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#define HAL_DCACHE_ENABLE() \
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CYG_MACRO_START \
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asm volatile ( \
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"mrc p15,0,r1,c7,c10,4;" /* drain write buffer */ \
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"mrc p15,0,r1,c1,c0,0;" \
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"orr r1,r1,#0x0007;" /* enable DCache (also ensures the */ \
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/* MMU and alignment faults are */ \
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/* enabled) */ \
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"mcr p15,0,r1,c1,c0,0;" \
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"mrc p15,0,r1,c1,c0,1;" \
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"bic r1,r1,#1;" \
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"mcr p15,0,r1,c1,c0,1;" \
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: \
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: \
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: "r1" /* Clobber list */ \
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); \
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CYG_MACRO_END
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// Disable the data cache (and invalidate it, required semanitcs)
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#define HAL_DCACHE_DISABLE() \
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CYG_MACRO_START \
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asm volatile ( \
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"mrc p15,0,r1,c1,c0,0;" /* disable cache */ \
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"bic r1,r1,#4;" \
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"mcr p15,0,r1,c1,c0,0;" \
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"mrc p15,0,r1,c1,c0,1;" /* disable coalescing */ \
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"orr r1,r1,#1;" \
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"mcr p15,0,r1,c1,c0,1;" \
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"mcr p15,0,r1,c7,c6,0;" /* invalidate data cache */ \
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/* cpuwait */ \
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"mrc p15,0,r1,c2,c0,0;" /* arbitrary read */ \
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"mov r1,r1;" \
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"sub pc,pc,#4;" \
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: \
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: \
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: "r1" /* Clobber list */ \
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); \
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CYG_MACRO_END
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// Query the state of the data cache
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#define HAL_DCACHE_IS_ENABLED(_state_) \
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CYG_MACRO_START \
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register int reg; \
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asm volatile ("mrc p15,0,%0,c1,c0,0" \
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: "=r"(reg) \
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: \
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/*:*/ \
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); \
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(_state_) = (0 != (4 & reg)); /* Bit 2 is DCache enable */ \
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CYG_MACRO_END
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// Flush the entire dcache (and then both TLBs, just in case)
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#define HAL_DCACHE_INVALIDATE_ALL() \
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CYG_MACRO_START /* this macro can discard dirty cache lines. */ \
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/* this macro can discard dirty cache lines. */ \
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asm volatile ( \
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"mcr p15,0,r1,c7,c6,0;" /* invalidate data cache */ \
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"mcr p15,0,r1,c8,c7,0;" /* flush I+D TLBs */ \
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: \
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: \
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: "r1" /* Clobber list */ \
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); \
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CYG_MACRO_END
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// DCACHE_FLUSH_AREA is defined if writeback caching is used. Otherwise
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// write-through is assumed.
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#ifdef DCACHE_FLUSH_AREA
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// Evict dirty lines from write-back caches
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#define HAL_DCACHE_EVICT() \
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CYG_MACRO_START \
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/* The best way to evict a dirty line is by using the */ \
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/* line allocate operation on non-existent memory. */ \
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asm volatile ( \
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"mov r0, %0;" /* cache flush region */ \
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"add r1, r0, #0x8800;" /* 32KB main + 2KB mini cache */ \
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"667: " \
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"mcr p15,0,r0,c7,c2,5;" /* allocate a line */ \
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"add r0, r0, #32;" /* 32 bytes/line */ \
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"teq r1, r0;" \
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"bne 667b;" \
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: \
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: "i" (DCACHE_FLUSH_AREA) \
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: "r0","r1" /* Clobber list */ \
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); \
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CYG_MACRO_END
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#else
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#define HAL_DCACHE_EVICT()
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#endif
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| 275 |
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// Synchronize the contents of the cache with memory.
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#define HAL_DCACHE_SYNC() \
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CYG_MACRO_START \
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| 278 |
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HAL_DCACHE_EVICT(); \
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asm volatile ( \
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| 280 |
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"mcr p15,0,r0,c7,c6,0;" /* invalidate data cache */ \
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/* cpuwait */ \
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| 282 |
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"mrc p15,0,r1,c2,c0,0;" /* arbitrary read */ \
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| 283 |
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"mov r1,r1;" \
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| 284 |
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"sub pc,pc,#4;" \
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| 285 |
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"mcr p15,0,r0,c7,c10,4;" /* and drain the write buffer */ \
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/* cpuwait */ \
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| 287 |
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"mrc p15,0,r1,c2,c0,0;" /* arbitrary read */ \
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"mov r1,r1;" \
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| 289 |
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"sub pc,pc,#4;" \
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"nop" \
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: \
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: \
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| 293 |
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: "r0","r1" /* Clobber list */ \
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); \
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CYG_MACRO_END
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| 296 |
|
|
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| 297 |
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// Set the data cache refill burst size
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| 298 |
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//#define HAL_DCACHE_BURST_SIZE(_size_)
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// This feature is not available on the XScale.
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| 300 |
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|
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| 301 |
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// Set the data cache write mode
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//#define HAL_DCACHE_WRITE_MODE( _mode_ )
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// This feature is not available on the XScale.
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| 304 |
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| 305 |
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#define HAL_DCACHE_WRITETHRU_MODE 0
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#define HAL_DCACHE_WRITEBACK_MODE 1
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|
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| 308 |
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// Get the current writeback mode - or only writeback mode if fixed
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| 309 |
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#ifdef DCACHE_FLUSH_AREA
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| 310 |
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#define HAL_DCACHE_QUERY_WRITE_MODE( _mode_ ) CYG_MACRO_START \
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| 311 |
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_mode_ = HAL_DCACHE_WRITEBACK_MODE; \
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| 312 |
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CYG_MACRO_END
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| 313 |
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#else
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#define HAL_DCACHE_QUERY_WRITE_MODE( _mode_ ) CYG_MACRO_START \
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| 315 |
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_mode_ = HAL_DCACHE_WRITETHRU_MODE; \
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| 316 |
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CYG_MACRO_END
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#endif
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| 318 |
|
|
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// Load the contents of the given address range into the data cache
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| 320 |
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// and then lock the cache so that it stays there.
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| 321 |
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|
//#define HAL_DCACHE_LOCK(_base_, _size_)
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| 322 |
|
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// This feature is not available on the XScale.
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| 323 |
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|
|
| 324 |
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// Undo a previous lock operation
|
| 325 |
|
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//#define HAL_DCACHE_UNLOCK(_base_, _size_)
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| 326 |
|
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// This feature is not available on the XScale.
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| 327 |
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|
| 328 |
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// Unlock entire cache
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| 329 |
|
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//#define HAL_DCACHE_UNLOCK_ALL()
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| 330 |
|
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// This feature is not available on the XScale.
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| 331 |
|
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|
| 332 |
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//-----------------------------------------------------------------------------
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| 333 |
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// Data cache line control
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| 334 |
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|
| 335 |
|
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// Allocate cache lines for the given address range without reading its
|
| 336 |
|
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// contents from memory.
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| 337 |
|
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//#define HAL_DCACHE_ALLOCATE( _base_ , _size_ )
|
| 338 |
|
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// This feature is not available on the XScale.
|
| 339 |
|
|
|
| 340 |
|
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// Write dirty cache lines to memory and invalidate the cache entries
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| 341 |
|
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// for the given address range.
|
| 342 |
|
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#define HAL_DCACHE_FLUSH( _base_ , _size_ ) \
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| 343 |
|
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CYG_MACRO_START \
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| 344 |
|
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HAL_DCACHE_STORE( _base_ , _size_ ); \
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| 345 |
|
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HAL_DCACHE_INVALIDATE( _base_ , _size_ ); \
|
| 346 |
|
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CYG_MACRO_END
|
| 347 |
|
|
|
| 348 |
|
|
// Invalidate cache lines in the given range without writing to memory.
|
| 349 |
|
|
#define HAL_DCACHE_INVALIDATE( _base_ , _size_ ) \
|
| 350 |
|
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CYG_MACRO_START \
|
| 351 |
|
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register int addr, enda; \
|
| 352 |
|
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for ( addr = (~(HAL_DCACHE_LINE_SIZE - 1)) & (int)(_base_), \
|
| 353 |
|
|
enda = (int)(_base_) + (_size_); \
|
| 354 |
|
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addr < enda ; \
|
| 355 |
|
|
addr += HAL_DCACHE_LINE_SIZE ) \
|
| 356 |
|
|
{ \
|
| 357 |
|
|
asm volatile ( \
|
| 358 |
|
|
"mcr p15,0,%0,c7,c6,1;" /* flush entry away */ \
|
| 359 |
|
|
: \
|
| 360 |
|
|
: "r"(addr) \
|
| 361 |
|
|
: "memory" \
|
| 362 |
|
|
); \
|
| 363 |
|
|
} \
|
| 364 |
|
|
CYG_MACRO_END
|
| 365 |
|
|
|
| 366 |
|
|
// Write dirty cache lines to memory for the given address range.
|
| 367 |
|
|
#define HAL_DCACHE_STORE( _base_ , _size_ ) \
|
| 368 |
|
|
CYG_MACRO_START \
|
| 369 |
|
|
register int addr, enda; \
|
| 370 |
|
|
for ( addr = (~(HAL_DCACHE_LINE_SIZE - 1)) & (int)(_base_), \
|
| 371 |
|
|
enda = (int)(_base_) + (_size_); \
|
| 372 |
|
|
addr < enda ; \
|
| 373 |
|
|
addr += HAL_DCACHE_LINE_SIZE ) \
|
| 374 |
|
|
{ \
|
| 375 |
|
|
asm volatile ("mcr p15,0,%0,c7,c10,1;" /* push entry to RAM */ \
|
| 376 |
|
|
: \
|
| 377 |
|
|
: "r"(addr) \
|
| 378 |
|
|
: "memory" \
|
| 379 |
|
|
); \
|
| 380 |
|
|
} \
|
| 381 |
|
|
/* and also drain the write buffer */ \
|
| 382 |
|
|
asm volatile ( \
|
| 383 |
|
|
"mov r1,#0;" \
|
| 384 |
|
|
"mcr p15,0,r1,c7,c10,4;" \
|
| 385 |
|
|
: \
|
| 386 |
|
|
: \
|
| 387 |
|
|
: "r1", "memory" /* Clobber list */ \
|
| 388 |
|
|
); \
|
| 389 |
|
|
CYG_MACRO_END
|
| 390 |
|
|
|
| 391 |
|
|
// Preread the given range into the cache with the intention of reading
|
| 392 |
|
|
// from it later.
|
| 393 |
|
|
//#define HAL_DCACHE_READ_HINT( _base_ , _size_ )
|
| 394 |
|
|
// This feature is available on the XScale, but due to tricky
|
| 395 |
|
|
// coherency issues with the read buffer (see XScale developer's
|
| 396 |
|
|
// manual) we don't bother to implement it here.
|
| 397 |
|
|
|
| 398 |
|
|
// Preread the given range into the cache with the intention of writing
|
| 399 |
|
|
// to it later.
|
| 400 |
|
|
//#define HAL_DCACHE_WRITE_HINT( _base_ , _size_ )
|
| 401 |
|
|
// This feature is not available on the XScale.
|
| 402 |
|
|
|
| 403 |
|
|
// Allocate and zero the cache lines associated with the given range.
|
| 404 |
|
|
//#define HAL_DCACHE_ZERO( _base_ , _size_ )
|
| 405 |
|
|
// This feature is not available on the XScale.
|
| 406 |
|
|
|
| 407 |
|
|
|
| 408 |
|
|
//-----------------------------------------------------------------------------
|
| 409 |
|
|
#endif // ifndef CYGONCE_HAL_CACHE_H
|
| 410 |
|
|
// End of hal_cache.h
|
