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[/] [openrisc/] [trunk/] [rtos/] [ecos-2.0/] [packages/] [hal/] [arm/] [xscale/] [iq80310/] [v2_0/] [src/] [diag/] [diag.c] - Blame information for rev 27

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//==========================================================================
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//
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//      diag.c
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//
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//      Additional RedBoot commands to run board diags.
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//
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//==========================================================================
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//####ECOSGPLCOPYRIGHTBEGIN####
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// -------------------------------------------
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// This file is part of eCos, the Embedded Configurable Operating System.
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// Copyright (C) 1998, 1999, 2000, 2001, 2002, 2003 Red Hat, Inc.
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//
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// eCos is free software; you can redistribute it and/or modify it under
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// the terms of the GNU General Public License as published by the Free
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// Software Foundation; either version 2 or (at your option) any later version.
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//
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// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or
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// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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// for more details.
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//
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// You should have received a copy of the GNU General Public License along
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// with eCos; if not, write to the Free Software Foundation, Inc.,
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// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
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//
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// As a special exception, if other files instantiate templates or use macros
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// or inline functions from this file, or you compile this file and link it
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// with other works to produce a work based on this file, this file does not
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// by itself cause the resulting work to be covered by the GNU General Public
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// License. However the source code for this file must still be made available
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// in accordance with section (3) of the GNU General Public License.
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//
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// This exception does not invalidate any other reasons why a work based on
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// this file might be covered by the GNU General Public License.
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//
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// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
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// at http://sources.redhat.com/ecos/ecos-license/
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// -------------------------------------------
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//####ECOSGPLCOPYRIGHTEND####
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//==========================================================================
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//#####DESCRIPTIONBEGIN####
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//
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// Author(s):    msalter
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// Contributors: msalter
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// Date:         2000-10-10
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// Purpose:      
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// Description:  
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//              
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// This code is part of RedBoot (tm).
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//
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//####DESCRIPTIONEND####
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//
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//==========================================================================
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#include <redboot.h>
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#include <cyg/io/eth/eth_drv.h>
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#include <cyg/hal/hal_arch.h>
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#include <cyg/hal/hal_intr.h>
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#include <cyg/hal/hal_cache.h>
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#include CYGHWR_MEMORY_LAYOUT_H
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#include <cyg/hal/hal_tables.h>
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#include "iq80310.h"
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int pci_config_cycle = 0;        /* skip exception handling when performing pci config cycle */
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static void do_hdwr_diag(int argc, char *argv[]);
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RedBoot_cmd("diag",
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            "Run board diagnostics",
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            "",
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            do_hdwr_diag
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    );
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void hdwr_diag (void);
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void do_hdwr_diag(int arg, char *argv[])
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{
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    hal_virtual_comm_table_t* __chan;
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    // Turn off interrupts on debug channel.
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    // All others should already be disabled.
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    __chan = CYGACC_CALL_IF_DEBUG_PROCS();
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    if (__chan)
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        CYGACC_COMM_IF_CONTROL(*__chan, __COMMCTL_IRQ_DISABLE);
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    HAL_INTERRUPT_MASK(eth_drv_int_vector());
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    hdwr_diag();
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}
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void __disableDCache(void)
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{
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    HAL_DCACHE_SYNC();
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    HAL_DCACHE_DISABLE();
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}
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void __enableDCache(void)
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{
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    HAL_DCACHE_ENABLE();
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}
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void _flushICache(void)
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{
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    HAL_ICACHE_INVALIDATE_ALL();
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}
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void __enableICache(void)
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{
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    HAL_ICACHE_ENABLE();
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}
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void __disableICache(void)
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{
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    HAL_ICACHE_DISABLE();
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}
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void _enableFiqIrq(void)
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{
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    asm ("mrc p15, 0, r0, c13, c0, 1;"
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         "orr r0, r0, #0x2000;"
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         "mrc p15, 0, r0, c13, c0, 1;"
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         "mrc p13, 0, r0, c0, c0, 0;"
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         "orr           r0, r0, #3;"
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         "mcr   p13, 0, r0, c0, c0, 0;"
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         : : );
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}
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void _enable_timer(void)
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{
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    asm("ldr r1, =0x00000005;"
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        "mcr p14, 0, r1, c0, c0, 0 ;"
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        : : : "r1" );
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}
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void _disable_timer(void)
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{
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    asm("ldr r1, =0x00000000;"
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        "mcr p14, 0, r1, c0, c0, 0 ;"
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        : : : "r1" );
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}
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void _usec_delay(void)
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{
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    asm ("ldr   r2, =0x258;"            /* 1 microsec = 600 clocks (600 MHz CPU core) */
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         "0: mrc p14, 0, r0, c1, c0, 0;"        /*read CCNT into r0 */
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         "cmp r2, r0;"  /* compare the current count */
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         "bpl   0b;" /* stay in loop until count is greater */
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         "mrc p14, 0, r1, c0, c0, 0;"
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         "orr   r1, r1, #4;"    /* clear the timer */
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         "mcr p14, 0, r1, c0, c0, 0 ;"
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         : : : "r0","r1","r2");
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}
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void _msec_delay(void)
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{
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    asm ("ldr   r2, =0x927c0;"  /* 1 millisec = 600,000 clocks (600 MHz CPU core) */
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         "0: mrc p14, 0, r0, c1, c0, 0;"        /*read CCNT into r0 */
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         "cmp r2, r0;"  /* compare the current count */
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         "bpl   0b;" /* stay in loop until count is greater */
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         "mrc p14, 0, r1, c0, c0, 0;"
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         "orr   r1, r1, #4;"    /* clear the timer */
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         "mcr p14, 0, r1, c0, c0, 0 ;"
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         : : : "r0","r1","r2");
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}
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unsigned int _read_timer(void)
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{
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    unsigned x;
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    asm("mrc p14, 0, %0, c1, c0, 0;" : "=r"(x) : );
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    return x;
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}
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