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#ifndef CYGONCE_IQ80310_H
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#define CYGONCE_IQ80310_H
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//=============================================================================
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//
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// iq80310.h - Cyclone Diagnostics
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//
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//=============================================================================
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//####ECOSGPLCOPYRIGHTBEGIN####
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// -------------------------------------------
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// This file is part of eCos, the Embedded Configurable Operating System.
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// Copyright (C) 1998, 1999, 2000, 2001, 2002, 2003 Red Hat, Inc.
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//
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// eCos is free software; you can redistribute it and/or modify it under
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// the terms of the GNU General Public License as published by the Free
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// Software Foundation; either version 2 or (at your option) any later version.
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//
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// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// for more details.
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//
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// You should have received a copy of the GNU General Public License along
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// with eCos; if not, write to the Free Software Foundation, Inc.,
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// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
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//
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// As a special exception, if other files instantiate templates or use macros
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// or inline functions from this file, or you compile this file and link it
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// with other works to produce a work based on this file, this file does not
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// by itself cause the resulting work to be covered by the GNU General Public
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// License. However the source code for this file must still be made available
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// in accordance with section (3) of the GNU General Public License.
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//
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// This exception does not invalidate any other reasons why a work based on
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// this file might be covered by the GNU General Public License.
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//
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// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
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// at http://sources.redhat.com/ecos/ecos-license/
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// -------------------------------------------
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//####ECOSGPLCOPYRIGHTEND####
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//=============================================================================
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//#####DESCRIPTIONBEGIN####
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//
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// Author(s): Scott Coulter, Jeff Frazier, Eric Breeden
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// Contributors:
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// Date: 2001-01-25
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// Purpose:
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// Description:
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//
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//####DESCRIPTIONEND####
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//
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//===========================================================================*/
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/******************************************************************************/
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/* iq80310.h - Header file for Cyclone IQ80310 Evaluation Board */
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/* */
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/* modification history */
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/* -------------------- */
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/* 07sep00, ejb, Written for IQ80310 Cygmon diagnostics */
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/* 18dec00 jwf */
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/* 09feb01 jwf */
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/******************************************************************************/
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#ifndef NULL
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#define NULL ((void *)0)
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#endif
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#ifndef ERROR
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#define ERROR -1
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#endif
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#ifndef OK
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#define OK 0
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#endif
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#ifndef TRUE
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#define TRUE 1
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#endif
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#ifndef FALSE
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#define FALSE 0
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#endif
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#include <cyg/infra/diag.h>
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#define printf diag_printf
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#define RAM_FUNC_SECT
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/* 02/09/01 jwf */
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/* Specify the operating system for version information retrieval */
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#define CYGNUS_CYGMON_OS FALSE
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#if CYGNUS_CYGMON_OS
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#define REDHAT_REDBOOT_OS FALSE
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#else
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#define REDHAT_REDBOOT_OS TRUE
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#endif
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typedef int STATUS;
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typedef unsigned char UCHAR;
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typedef unsigned char UINT8;
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typedef unsigned short USHORT;
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typedef unsigned short UINT16;
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typedef unsigned long ULONG;
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typedef unsigned int UINT;
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typedef unsigned int UINT32;
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typedef int (*INTFUNCPTR) (int);
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typedef int (*FUNCPTR) (void);
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typedef void (*VOIDFUNCPTR) (int);
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/* board specific definitions */
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#define MEMBASE_DRAM 0xa0000000
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/* UART definitions */
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#define SCALE 0x10000 /* distance between port addresses */
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#define TERMINAL 0xfe800000 /* Terminal base address */
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#define ACCESS_DELAY 5
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#define DFLTPORT 0 /* channel 2 on 16C552 */
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#define XTAL 1843200 /* frequency of baud rate generation crystal */
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/* Backplane Detect Register */
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//#define BACKPLANE_DET_REG (volatile unsigned char *)0xfe870000
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#define BP_HOST_BIT 0x1
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/* PAL-based external timer definitions */
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//#define TIMER_LA0_REG_ADDR (volatile unsigned char *)0xfe880000
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//#define TIMER_LA1_REG_ADDR (volatile unsigned char *)0xfe890000
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//#define TIMER_LA2_REG_ADDR (volatile unsigned char *)0xfe8a0000
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//#define TIMER_LA3_REG_ADDR (volatile unsigned char *)0xfe8b0000
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//#define TIMER_ENABLE_REG_ADDR (volatile unsigned char *)0xfe8c0000
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#define TIMER_COUNT_MASK 0x5f /* 6 bits of timer data with the MSB in bit 6 not bit 5 */
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#define TIMER_CNT_ENAB 0x1
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#define TIMER_INT_ENAB 0x2
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#define EXT_TIMER_CLK_FREQ 33000000 /* external timer runs at 33 MHz */
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#define TICKS_10MSEC 100 /* 10msec = 100 ticks/sec */
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#define EXT_TIMER_10MSEC_COUNT (EXT_TIMER_CLK_FREQ / TICKS_10MSEC)
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#define TICKS_5MSEC 200 /* 5msec = 200 ticks/sec */
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#define EXT_TIMER_5MSEC_COUNT (EXT_TIMER_CLK_FREQ / TICKS_5MSEC)
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#define EXT_TIMER_CNT_ENAB() (*TIMER_ENABLE_REG_ADDR |= TIMER_CNT_ENAB)
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#define EXT_TIMER_CNT_DISAB() (*TIMER_ENABLE_REG_ADDR &= ~TIMER_CNT_ENAB)
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#define EXT_TIMER_INT_ENAB() (*TIMER_ENABLE_REG_ADDR |= TIMER_INT_ENAB)
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#define EXT_TIMER_INT_DISAB() (*TIMER_ENABLE_REG_ADDR &= ~TIMER_INT_ENAB)
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/* 80312 Interrupt Status Registers */
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#define X3ISR_ADDR 0xfe820000 /* XINT3 (external interrupts) Status Register */
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#define X3MASK_ADDR 0xfe860000 /* XINT3 Mask Register */
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/* 12/18/00 jwf */
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/* CPLD Read only Registers */
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#define BOARD_REV_REG_ADDR (volatile unsigned char *)0xfe830000 /* Board Revision Register, xxxxbbbb=0x2<-->Rev B Board, Note: This was not implemented in the CPLD for board revisions A,B,C and D. */
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#define BOARD_REV_E (unsigned char)0x5 /* BOARD REV E */
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#define BOARD_REV_MASK (unsigned char)0xf /* use only b0-b3 */
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#define CPLD_REV_REG_ADDR (volatile unsigned char *)0xfe840000 /* CPLD Revision Register, data examples: xxxxbbbb=0x3<-->Rev C CPLD(used on PCI-700 Rev D Board), xxxxbbbb=0x4<-->Rev D CPLD(used on PCI-700 Rev E Board) */
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#define SINT_REG_ADDR (volatile unsigned char *)0xfe850000 /* SINTA-SINTC secondary PCI interrupt status register */
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/* SINT_REG_ADDR Register Interrupt Status bit definitions */
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#define SINTA_INT (unsigned char)0x1 /* b0=1, Secondary PCI (S_INTA) Interrupt Pending */
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#define SINTB_INT (unsigned char)0x2 /* b1=1, Secondary PCI (S_INTB) Interrupt Pending */
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#define SINTC_INT (unsigned char)0x4 /* b2=1, Secondary PCI (S_INTC) Interrupt Pending */
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#define SINT_MASK (unsigned char)0x7 /* isolate bits b0-b2 */
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#define RI_MASK (unsigned char)0x40 /* use to isolate bit 6, Ring Indicator, of MSR in UART 2 */
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/* Intel 28F640J3A Strata Flash Memory Definitions */
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#define NUM_FLASH_BANKS 1 /* number of flash banks, there is only 1 flash memory chip on the pci-700 board */
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#define FLASH_WIDTH 1 /* width of flash in bytes */
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#define FLASH_BASE_ADDR 0x00000000 /* base address of flash block 0, avoid this area, vectors and cygmon code occupy addresses 0x2000h-0x28000h */
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#define DEV_CODE_ADDR (0x00000001 << 1) /* address of Device Code in Flash memory, note that address bit A0 is not used, must shift 0x00000001<<1=0x00000002 */
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/* 10/17/00 jwf */
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#define FLASH_BLK4_BASE_ADDR 0x80000
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#define FLASH_TOP_ADDR 0x7fffff /* last address of last block of flash memory */
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#define FLASH_ADDR 0x00000000 /* base address of flash block 0, avoid this area, vectors and cygmon code occupy addresses 0x2000h-0x28000h */
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#define FLASH_ADDR_INCR 0x00020000 /* address offset of each flash block, 128K block, byte-wide (X8) mode, device address range 0-7fffff */
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#define VALID_FLASH_ADDR 0x00000000 /* base address of flash block 0 */
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#define FLASH_TIME_ADJUST 1 /* delay adjustment factor for delay times */
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/* 10/17/00 jwf */
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#define RESERVED_AREA1 0x0 /* 0h-1ffffh is partially occupied by Cygnus Cygmon monitor and debug code */
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#define RESERVED_AREA2 0x20000 /* 20000h-3ffffh is partially occupied by Cygnus Cygmon monitor and debug code */
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#define RESERVED_AREA3 0x40000 /* 40000h-5ffffh is partially occupied by Cygnus Cygmon debug code */
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#define RESERVED_AREA4 0x60000 /* 60000h-7ffffh is partially occupied by Cygnus Cygmon debug code */
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#define RESERVED_AREA_SIZE 0x80000 /* 20000h * 4h */
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/* Definitions for Battery Backup SDRAM memory test */
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#define SDRAM_BATTERY_TEST_BASE 0xA1FFFFF0 /* base address of last 16 memory locations in 32MB SDRAM */
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/* #define BATTERY_TEST_PATTERN 0xBAEBAEBA */
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#define BATTERY_TEST_PATTERN 0x55555555
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/* 02/09/01 jwf */
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/* Use a base address set to the fourth memory location from the last memory location */
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/* in a 32MB SDRAM DIMM to store the 80200 Coyanosa ID 32 bit data */
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#define COYANOSA_ID_BASE_ADDR 0xA1FFFFFC
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/* Definitions for data types and constants used in Flash.c */
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typedef unsigned long ADDR;
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#define NO_ADDR ((ADDR)0x800000) /* last address of Flash memory + 1 */
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#ifndef ERR
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#define ERR -1
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#endif
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/* Error code Constants */
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#define E_EEPROM_ADDR 12
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#define E_EEPROM_PROG 13
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#define E_EEPROM_FAIL 14
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#define E_NO_FLASH 29
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/* 10/17/00 jwf */
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#define BREEZE_BLOCK_0 0x0
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#define NUM_BREEZE_BLOCKS 4
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#define NUM_FLASH_BLOCKS 64
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/* 80310 IRQ Interrupt Identifiers (used for connecting and disconnecting ISRs) */
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#define DMA0_INT_ID 0
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#define DMA1_INT_ID 1
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#define DMA2_INT_ID 2
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#define PM_INT_ID 3
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#define AA_INT_ID 4
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#define I2C_INT_ID 5
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#define MU_INT_ID 6
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#define PATU_INT_ID 7
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#define TIMER_INT_ID 8
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#define ENET_INT_ID 9
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#define UART1_INT_ID 10
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#define UART2_INT_ID 11
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#define SINTA_INT_ID 12
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#define SINTB_INT_ID 13
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#define SINTC_INT_ID 14
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#define SINTD_INT_ID 15
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/* XINT3 External Interrupt Status and Mask bit definitions */
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#define TIMER_INT (1 << 0) /* Timer Interrupt Pending */
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#define ENET_INT (1 << 1) /* Ethernet Interrupt Pending */
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#define UART1_INT (1 << 2) /* UART1 Interrupt Pending */
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#define UART2_INT (1 << 3) /* UART2 Interrupt Pending */
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#define SINTD_INT (1 << 4) /* Secondary PCI (S_INTD) Interrupt Pending */
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/* XINT6 Interrupt Status bit definitions */
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#define DMA0_INT (1 << 0) /* DMA Channel 0 Interrupt Pending */
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#define DMA1_INT (1 << 2) /* DMA Channel 1 Interrupt Pending */
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#define DMA2_INT (1 << 3) /* DMA Channel 2 Interrupt Pending */
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#define PM_INT (1 << 5) /* Performance Monitoring Unit Interrupt Pending */
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#define AA_INT (1 << 6) /* Application Accelerator Interrupt Pending */
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/* XINT7 Interrupt Status bit definitions */
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#define I2C_INT (1 << 1) /* I2C Interrupt Pending */
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#define MU_INT (1 << 2) /* Messaging Unit Interrupt Pending */
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#define PATU_INT (1 << 3) /* Primary ATU / BIST Start Interrupt Pending */
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/* NISR bit definitions */
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#define MCU_ERROR (1 << 0) /* 80960 core Error within internal memory controller */
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#define PATU_ERROR (1 << 1) /* Primary ATU Error (PCI or local bus error) */
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#define SATU_ERROR (1 << 2) /* Secondary ATU Error (PCI or local bus error) */
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#define PBRIDGE_ERROR (1 << 3) /* Primary Bridge Interface Error */
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#define SBRIDGE_ERROR (1 << 4) /* Secondary Bridge Interface Error */
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#define DMA_0_ERROR (1 << 5) /* DMA Channel 0 Error (PCI or local bus error) */
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#define DMA_1_ERROR (1 << 6) /* DMA Channel 1 Error (PCI or local bus error) */
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#define DMA_2_ERROR (1 << 7) /* DMA Channel 2 Error (PCI or local bus error) */
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#define MU_ERROR (1 << 8) /* Messaging Unit NMI interrupt */
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#define AAU_ERROR (1 << 10) /* Application Accelerator Unit Error */
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#define BIU_ERROR (1 << 11) /* Bus Interface Unit Error */
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| 274 |
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| 275 |
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| 276 |
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/* macros to clear (S/P PCI Status register bits) */
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#define CLEAR_PATU_STATUS() (*(volatile UINT16 *)PATUSR_ADDR |= 0xf900)
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#define CLEAR_SATU_STATUS() (*(volatile UINT16 *)SATUSR_ADDR |= 0xf900)
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#define CLEAR_PBRIDGE_STATUS() (*(volatile UINT16 *)PSR_ADDR |= 0xf900)
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#define CLEAR_SBRIDGE_STATUS() (*(volatile UINT16 *)SSR_ADDR |= 0xf900)
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/*** Yavapai Registers ***/
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| 290 |
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/* PCI-to-PCI Bridge Unit 0000 1000H through 0000 10FFH */
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#define VIDR_ADDR 0x00001000
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#define DIDR_ADDR 0x00001002
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#define PCR_ADDR 0x00001004
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#define PSR_ADDR 0x00001006
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#define RIDR_ADDR 0x00001008
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#define CCR_ADDR 0x00001009
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#define CLSR_ADDR 0x0000100C
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#define PLTR_ADDR 0x0000100D
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#define HTR_ADDR 0x0000100E
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|
|
/* Reserved 0x0000100F through 0x00001017 */
|
| 301 |
|
|
#define PBNR_ADDR 0x00001018
|
| 302 |
|
|
#define SBNR_ADDR 0x00001019
|
| 303 |
|
|
#define SUBBNR_ADDR 0x0000101A
|
| 304 |
|
|
#define SLTR_ADDR 0x0000101B
|
| 305 |
|
|
#define IOBR_ADDR 0x0000101C
|
| 306 |
|
|
#define IOLR_ADDR 0x0000101D
|
| 307 |
|
|
#define SSR_ADDR 0x0000101E
|
| 308 |
|
|
#define MBR_ADDR 0x00001020
|
| 309 |
|
|
#define MLR_ADDR 0x00001022
|
| 310 |
|
|
#define PMBR_ADDR 0x00001024
|
| 311 |
|
|
#define PMLR_ADDR 0x00001026
|
| 312 |
|
|
/* Reserved 0x00001028 through 0x00001033 */
|
| 313 |
|
|
#define BSVIR_ADDR 0x00001034
|
| 314 |
|
|
#define BSIR_ADDR 0x00001036
|
| 315 |
|
|
/* Reserved 0x00001038 through 0x0000103D */
|
| 316 |
|
|
#define BCR_ADDR 0x0000103E
|
| 317 |
|
|
#define EBCR_ADDR 0x00001040
|
| 318 |
|
|
#define SISR_ADDR 0x00001042
|
| 319 |
|
|
#define PBISR_ADDR 0x00001044
|
| 320 |
|
|
#define SBISR_ADDR 0x00001048
|
| 321 |
|
|
#define SACR_ADDR 0x0000104C
|
| 322 |
|
|
#define PIRSR_ADDR 0x00001050
|
| 323 |
|
|
#define SIOBR_ADDR 0x00001054
|
| 324 |
|
|
#define SIOLR_ADDR 0x00001055
|
| 325 |
|
|
#define SCCR_ADDR 0x00001056 /* EAS inconsistent */
|
| 326 |
|
|
#define SMBR_ADDR 0x00001058
|
| 327 |
|
|
#define SMLR_ADDR 0x0000105A
|
| 328 |
|
|
#define SDER_ADDR 0x0000105C
|
| 329 |
|
|
#define QCR_ADDR 0x0000105E
|
| 330 |
|
|
#define CDTR_ADDR 0x00001060 /* EAS inconsistent */
|
| 331 |
|
|
/* Reserved 0x00001064 through 0x000010FFH */
|
| 332 |
|
|
|
| 333 |
|
|
/* Performance Monitoring Unit 0000 1100H through 0000 11FFH */
|
| 334 |
|
|
#define GMTR_ADDR 0x00001100
|
| 335 |
|
|
#define ESR_ADDR 0x00001104
|
| 336 |
|
|
#define EMISR_ADDR 0x00001108
|
| 337 |
|
|
/* Reserved 0x0000110C */ /* EAS inconsistent */
|
| 338 |
|
|
#define GTSR_ADDR 0x00001110 /* EAS inconsistent */
|
| 339 |
|
|
#define PECR1_ADDR 0x00001114 /* EAS inconsistent */
|
| 340 |
|
|
#define PECR2_ADDR 0x00001118 /* EAS inconsistent */
|
| 341 |
|
|
#define PECR3_ADDR 0x0000111C /* EAS inconsistent */
|
| 342 |
|
|
#define PECR4_ADDR 0x00001120 /* EAS inconsistent */
|
| 343 |
|
|
#define PECR5_ADDR 0x00001124 /* EAS inconsistent */
|
| 344 |
|
|
#define PECR6_ADDR 0x00001128 /* EAS inconsistent */
|
| 345 |
|
|
#define PECR7_ADDR 0x0000112C /* EAS inconsistent */
|
| 346 |
|
|
#define PECR8_ADDR 0x00001130 /* EAS inconsistent */
|
| 347 |
|
|
#define PECR9_ADDR 0x00001134 /* EAS inconsistent */
|
| 348 |
|
|
#define PECR10_ADDR 0x00001138 /* EAS inconsistent */
|
| 349 |
|
|
#define PECR11_ADDR 0x0000113C /* EAS inconsistent */
|
| 350 |
|
|
#define PECR12_ADDR 0x00001140 /* EAS inconsistent */
|
| 351 |
|
|
#define PECR13_ADDR 0x00001144 /* EAS inconsistent */
|
| 352 |
|
|
#define PECR14_ADDR 0x00001148 /* EAS inconsistent */
|
| 353 |
|
|
/* Reserved 0x0000104C through 0x000011FFH */ /* EAS inconsistent */
|
| 354 |
|
|
|
| 355 |
|
|
/* Address Translation Unit 0000 1200H through 0000 12FFH */
|
| 356 |
|
|
#define ATUVID_ADDR 0x00001200
|
| 357 |
|
|
#define ATUDID_ADDR 0x00001202
|
| 358 |
|
|
#define PATUCMD_ADDR 0x00001204
|
| 359 |
|
|
#define PATUSR_ADDR 0x00001206
|
| 360 |
|
|
#define ATURID_ADDR 0x00001208
|
| 361 |
|
|
#define ATUCCR_ADDR 0x00001209
|
| 362 |
|
|
#define ATUCLSR_ADDR 0x0000120C
|
| 363 |
|
|
#define ATULT_ADDR 0x0000120D
|
| 364 |
|
|
#define ATUHTR_ADDR 0x0000120E
|
| 365 |
|
|
#define ATUBISTR_ADDR 0x0000120F
|
| 366 |
|
|
#define PIABAR_ADDR 0x00001210
|
| 367 |
|
|
/* Reserved 0x00001214 through 0x0000122B */
|
| 368 |
|
|
#define ASVIR_ADDR 0x0000122C
|
| 369 |
|
|
#define ASIR_ADDR 0x0000122E
|
| 370 |
|
|
#define ERBAR_ADDR 0x00001230
|
| 371 |
|
|
/* Reserved 0x00001234 */
|
| 372 |
|
|
/* Reserved 0x00001238 */
|
| 373 |
|
|
#define ATUILR_ADDR 0x0000123C
|
| 374 |
|
|
#define ATUIPR_ADDR 0x0000123D
|
| 375 |
|
|
#define ATUMGNT_ADDR 0x0000123E
|
| 376 |
|
|
#define ATUMLAT_ADDR 0x0000123F
|
| 377 |
|
|
#define PIALR_ADDR 0x00001240
|
| 378 |
|
|
#define PIATVR_ADDR 0x00001244
|
| 379 |
|
|
#define SIABAR_ADDR 0x00001248
|
| 380 |
|
|
#define SIALR_ADDR 0x0000124C
|
| 381 |
|
|
#define SIATVR_ADDR 0x00001250
|
| 382 |
|
|
#define POMWVR_ADDR 0x00001254
|
| 383 |
|
|
/* Reserved 0x00001258 */
|
| 384 |
|
|
#define POIOWVR_ADDR 0x0000125C
|
| 385 |
|
|
#define PODWVR_ADDR 0x00001260
|
| 386 |
|
|
#define POUDR_ADDR 0x00001264
|
| 387 |
|
|
#define SOMWVR_ADDR 0x00001268
|
| 388 |
|
|
#define SOIOWVR_ADDR 0x0000126C
|
| 389 |
|
|
/* Reserved 0x00001270 */
|
| 390 |
|
|
#define ERLR_ADDR 0x00001274
|
| 391 |
|
|
#define ERTVR_ADDR 0x00001278
|
| 392 |
|
|
/* Reserved 0x0000127C */
|
| 393 |
|
|
/* Reserved 0x00001280 */
|
| 394 |
|
|
/* Reserved 0x00001284 */
|
| 395 |
|
|
#define ATUCR_ADDR 0x00001288
|
| 396 |
|
|
/* Reserved 0x0000128C */
|
| 397 |
|
|
#define PATUISR_ADDR 0x00001290
|
| 398 |
|
|
#define SATUISR_ADDR 0x00001294
|
| 399 |
|
|
#define SATUCMD_ADDR 0x00001298
|
| 400 |
|
|
#define SATUSR_ADDR 0x0000129A
|
| 401 |
|
|
#define SODWVR_ADDR 0x0000129C
|
| 402 |
|
|
#define SOUDR_ADDR 0x000012A0
|
| 403 |
|
|
#define POCCAR_ADDR 0x000012A4
|
| 404 |
|
|
#define SOCCAR_ADDR 0x000012A8
|
| 405 |
|
|
#define POCCDR_ADDR 0x000012AC
|
| 406 |
|
|
#define SOCCDR_ADDR 0x000012B0
|
| 407 |
|
|
#define PAQCR_ADDR 0x000012B4
|
| 408 |
|
|
#define SAQCR_ADDR 0x000012B8
|
| 409 |
|
|
#define PAIMR_ADDR 0x000012BC
|
| 410 |
|
|
#define SAIMR_ADDR 0x000012C0
|
| 411 |
|
|
/* Reserved 0x000012C4 through 0x000012FF */
|
| 412 |
|
|
|
| 413 |
|
|
/* Messaging Unit 0000 1300H through 0000 130FH */
|
| 414 |
|
|
#define IMR0_ADDR 0x00001310
|
| 415 |
|
|
#define IMR1_ADDR 0x00001314
|
| 416 |
|
|
#define OMR0_ADDR 0x00001318
|
| 417 |
|
|
#define OMR1_ADDR 0x0000131C
|
| 418 |
|
|
#define IDR_ADDR 0x00001320
|
| 419 |
|
|
#define IISR_ADDR 0x00001324
|
| 420 |
|
|
#define IIMR_ADDR 0x00001328
|
| 421 |
|
|
#define ODR_ADDR 0x0000132C
|
| 422 |
|
|
#define OISR_ADDR 0x00001330
|
| 423 |
|
|
#define OIMR_ADDR 0x00001334
|
| 424 |
|
|
/* Reserved 0x00001338 through 0x0000134F */
|
| 425 |
|
|
#define MUCR_ADDR 0x00001350
|
| 426 |
|
|
#define QBAR_ADDR 0x00001354
|
| 427 |
|
|
/* Reserved 0x00001358 */
|
| 428 |
|
|
/* Reserved 0x0000135C */
|
| 429 |
|
|
#define IFHPR_ADDR 0x00001360
|
| 430 |
|
|
#define IFTPR_ADDR 0x00001364
|
| 431 |
|
|
#define IPHPR_ADDR 0x00001368
|
| 432 |
|
|
#define IPTPR_ADDR 0x0000136C
|
| 433 |
|
|
#define OFHPR_ADDR 0x00001370
|
| 434 |
|
|
#define OFTPR_ADDR 0x00001374
|
| 435 |
|
|
#define OPHPR_ADDR 0x00001378
|
| 436 |
|
|
#define OPTPR_ADDR 0x0000137C
|
| 437 |
|
|
#define IAR_ADDR 0x00001380
|
| 438 |
|
|
/* Reserved 0x00001384 through 0x000013FF */
|
| 439 |
|
|
|
| 440 |
|
|
/* DMA Controller 0000 1400H through 0000 14FFH */
|
| 441 |
|
|
#define CCR0_ADDR 0x00001400
|
| 442 |
|
|
#define CSR0_ADDR 0x00001404
|
| 443 |
|
|
/* Reserved 0x00001408 */
|
| 444 |
|
|
#define DAR0_ADDR 0x0000140C
|
| 445 |
|
|
#define NDAR0_ADDR 0x00001410
|
| 446 |
|
|
#define PADR0_ADDR 0x00001414
|
| 447 |
|
|
#define PUADR0_ADDR 0x00001418
|
| 448 |
|
|
#define LADR0_ADDR 0x0000141C
|
| 449 |
|
|
#define BCR0_ADDR 0x00001420
|
| 450 |
|
|
#define DCR0_ADDR 0x00001424
|
| 451 |
|
|
/* Reserved 0x00001428 through 0x0000143F */
|
| 452 |
|
|
#define CCR1_ADDR 0x00001440
|
| 453 |
|
|
#define CSR1_ADDR 0x00001444
|
| 454 |
|
|
/* Reserved 0x00001448 */
|
| 455 |
|
|
#define DAR1_ADDR 0x0000144C
|
| 456 |
|
|
#define NDAR1_ADDR 0x00001450
|
| 457 |
|
|
#define PADR1_ADDR 0x00001454
|
| 458 |
|
|
#define PUADR1_ADDR 0x00001458
|
| 459 |
|
|
#define LADR1_ADDR 0x0000145C
|
| 460 |
|
|
#define BCR1_ADDR 0x00001460
|
| 461 |
|
|
#define DCR1_ADDR 0x00001464
|
| 462 |
|
|
/* Reserved 0x00001468 through 0x0000147F */
|
| 463 |
|
|
#define CCR2_ADDR 0x00001480
|
| 464 |
|
|
#define CSR2_ADDR 0x00001484
|
| 465 |
|
|
/* Reserved 0x00001488 */
|
| 466 |
|
|
#define DAR2_ADDR 0x0000148C
|
| 467 |
|
|
#define NDAR2_ADDR 0x00001490
|
| 468 |
|
|
#define PADR2_ADDR 0x00001494
|
| 469 |
|
|
#define PUADR2_ADDR 0x00001498
|
| 470 |
|
|
#define LADR2_ADDR 0x0000149C
|
| 471 |
|
|
#define BCR2_ADDR 0x000014A0
|
| 472 |
|
|
#define DCR2_ADDR 0x000014A4
|
| 473 |
|
|
/* Reserved 0x000014A8 through 0x000014FF */
|
| 474 |
|
|
|
| 475 |
|
|
/* Memory Controller 0000 1500H through 0000 15FFH */
|
| 476 |
|
|
#define SDIR_ADDR 0x00001500
|
| 477 |
|
|
#define SDCR_ADDR 0x00001504
|
| 478 |
|
|
#define SDBR_ADDR 0x00001508
|
| 479 |
|
|
#define SBR0_ADDR 0x0000150C
|
| 480 |
|
|
#define SBR1_ADDR 0x00001510
|
| 481 |
|
|
#define SDPR0_ADDR 0x00001514
|
| 482 |
|
|
#define SDPR1_ADDR 0x00001518
|
| 483 |
|
|
#define SDPR2_ADDR 0x0000151C
|
| 484 |
|
|
#define SDPR3_ADDR 0x00001520
|
| 485 |
|
|
#define SDPR4_ADDR 0x00001524
|
| 486 |
|
|
#define SDPR5_ADDR 0x00001528
|
| 487 |
|
|
#define SDPR6_ADDR 0x0000152C
|
| 488 |
|
|
#define SDPR7_ADDR 0x00001530
|
| 489 |
|
|
#define ECCR_ADDR 0x00001534
|
| 490 |
|
|
#define ELOG0_ADDR 0x00001538
|
| 491 |
|
|
#define ELOG1_ADDR 0x0000153C
|
| 492 |
|
|
#define ECAR0_ADDR 0x00001540
|
| 493 |
|
|
#define ECAR1_ADDR 0x00001544
|
| 494 |
|
|
#define ECTST_ADDR 0x00001548
|
| 495 |
|
|
#define FEBR0_ADDR 0x0000154C
|
| 496 |
|
|
#define FEBR1_ADDR 0x00001550
|
| 497 |
|
|
#define FBSR0_ADDR 0x00001554
|
| 498 |
|
|
#define FBSR1_ADDR 0x00001558
|
| 499 |
|
|
#define FWSR0_ADDR 0x0000155C
|
| 500 |
|
|
#define FWSR1_ADDR 0x00001560
|
| 501 |
|
|
#define MCISR_ADDR 0x00001564
|
| 502 |
|
|
#define RFR_ADDR 0x00001568
|
| 503 |
|
|
/* Reserved 0x0000156C through 0x000015FF */
|
| 504 |
|
|
|
| 505 |
|
|
/* Arbitration Control Unit 0000 1600H through 0000 167FH */
|
| 506 |
|
|
#define IACR_ADDR 0x00001600
|
| 507 |
|
|
#define MLTR_ADDR 0x00001604
|
| 508 |
|
|
#define MTTR_ADDR 0x00001608
|
| 509 |
|
|
/* Reserved 0x0000160C through 0x0000163F */
|
| 510 |
|
|
|
| 511 |
|
|
/* Bus Interface Control Unit 0000 1640H through 0000 167FH */
|
| 512 |
|
|
#define BIUCR_ADDR 0x00001640
|
| 513 |
|
|
#define BIUISR_ADDR 0x00001644
|
| 514 |
|
|
/* Reserved 0x00001648 through 0x0000167F */
|
| 515 |
|
|
|
| 516 |
|
|
/* I2C Bus Interface Unit 0000 1680H through 0000 16FFH */
|
| 517 |
|
|
#define ICR_ADDR 0x00001680
|
| 518 |
|
|
#define ISR_ADDR 0x00001684
|
| 519 |
|
|
#define ISAR_ADDR 0x00001688
|
| 520 |
|
|
#define IDBR_ADDR 0x0000168C
|
| 521 |
|
|
#define ICCR_ADDR 0x00001690
|
| 522 |
|
|
#define IBMR_ADDR 0x00001694
|
| 523 |
|
|
/* Reserved 0x00001698 through 0x000016FF */
|
| 524 |
|
|
|
| 525 |
|
|
/* PCI And Peripheral Interrupt Controller 0000 1700H through 0000 17FFH */
|
| 526 |
|
|
#define NISR_ADDR 0x00001700
|
| 527 |
|
|
#define X7ISR_ADDR 0x00001704
|
| 528 |
|
|
#define X6ISR_ADDR 0x00001708
|
| 529 |
|
|
#define PDIDR_ADDR 0x00001710 /* EAS inconsistent */
|
| 530 |
|
|
/* Reserved 0x00001714 through 0x0000177F */
|
| 531 |
|
|
|
| 532 |
|
|
/* Application Accelerator Unit 0000 1800H through 0000 18FFH */
|
| 533 |
|
|
#define ACR_ADDR 0x00001800
|
| 534 |
|
|
#define ASR_ADDR 0x00001804
|
| 535 |
|
|
#define ADAR_ADDR 0x00001808
|
| 536 |
|
|
#define ANDAR_ADDR 0x0000180C
|
| 537 |
|
|
#define SAR1_ADDR 0x00001810
|
| 538 |
|
|
#define SAR2_ADDR 0x00001814
|
| 539 |
|
|
#define SAR3_ADDR 0x00001818
|
| 540 |
|
|
#define SAR4_ADDR 0x0000181C
|
| 541 |
|
|
#define DAR_ADDR 0x00001820
|
| 542 |
|
|
#define ABCR_ADDR 0x00001824
|
| 543 |
|
|
#define ADCR_ADDR 0x00001828
|
| 544 |
|
|
#define SAR5_ADDR 0x0000182C
|
| 545 |
|
|
#define SAR6_ADDR 0x00001830
|
| 546 |
|
|
#define SAR7_ADDR 0x00001834
|
| 547 |
|
|
#define SAR8_ADDR 0x00001838
|
| 548 |
|
|
|
| 549 |
|
|
/* Reserved 0x0000183C through 0x000018FF */
|
| 550 |
|
|
|
| 551 |
|
|
|
| 552 |
|
|
#endif /* CYGONCE_IQ80310_H */
|
