OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [rtos/] [ecos-2.0/] [packages/] [hal/] [arm/] [xscale/] [iq80310/] [v2_0/] [src/] [diag/] [irq.S] - Blame information for rev 565

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 27 unneback
//=============================================================================
2
//
3
//      irq.S - Cyclone Diagnostics
4
//
5
//=============================================================================
6
//####ECOSGPLCOPYRIGHTBEGIN####
7
// -------------------------------------------
8
// This file is part of eCos, the Embedded Configurable Operating System.
9
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
10
//
11
// eCos is free software; you can redistribute it and/or modify it under
12
// the terms of the GNU General Public License as published by the Free
13
// Software Foundation; either version 2 or (at your option) any later version.
14
//
15
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
16
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
17
// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
18
// for more details.
19
//
20
// You should have received a copy of the GNU General Public License along
21
// with eCos; if not, write to the Free Software Foundation, Inc.,
22
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
23
//
24
// As a special exception, if other files instantiate templates or use macros
25
// or inline functions from this file, or you compile this file and link it
26
// with other works to produce a work based on this file, this file does not
27
// by itself cause the resulting work to be covered by the GNU General Public
28
// License. However the source code for this file must still be made available
29
// in accordance with section (3) of the GNU General Public License.
30
//
31
// This exception does not invalidate any other reasons why a work based on
32
// this file might be covered by the GNU General Public License.
33
//
34
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
35
// at http://sources.redhat.com/ecos/ecos-license/
36
// -------------------------------------------
37
//####ECOSGPLCOPYRIGHTEND####
38
//=============================================================================
39
//#####DESCRIPTIONBEGIN####
40
//
41
// Author(s):   Scott Coulter, Jeff Frazier, Eric Breeden
42
// Contributors:
43
// Date:        2001-01-25
44
// Purpose:
45
// Description:
46
//
47
//####DESCRIPTIONEND####
48
//
49
//===========================================================================*/
50
 
51
/*
52
 * Low-lebvel interrupt support for IQ80310 diags
53
 */
54
        .extern iq80310_irq_handler
55
        .extern iq80310_fiq_handler
56
 
57
        .text
58
        .globl __diag_IRQ
59
  __diag_IRQ:
60
        ldr     sp, =__irq_stack    /* point stack pointer at IRQ stack */
61
        sub     lr, lr, #4         /* adjust lr (return to last address) */
62
        stmfd   sp!, {r12, lr}     /* push r12 and link reg onto stack */
63
        mrs     r12, spsr          /* store spsr in r12 */
64
        stmfd   sp!, {r12}         /* push spsr onto stack */
65
        stmfd   sp!, {r0-r11}      /* push all registers onto stack */
66
        bl      iq80310_irq_handler
67
        ldmfd   sp!, {r0-r12}      /* restore r0 thru r12 */
68
        msr     spsr, r12          /* restore SPSR */
69
        ldmfd   sp!, {r12,pc}^     /* restore r12 and PC, return */
70
 
71
        .globl __diag_FIQ
72
  __diag_FIQ:
73
        /* Cyclone FIQ handler */
74
        /* save registers onto stack */
75
        ldr     sp, =__fiq_stack        /* point stack pointer at FIQ stack */
76
        sub     lr, lr, #4      /* adjust link register (return to last address) */
77
        stmfd   sp!, {r12, lr}  /* push r12 and link reg onto stack */
78
        mrs     r12, spsr       /* store spsr in r12 */
79
        stmfd   sp!, {r12}      /* push spsr onto stack */
80
        stmfd   sp!, {r0-r7}    /* push r0 thru r7 (r8 - r14 are banked) */
81
        bl      iq80310_fiq_handler
82
        /* restore registers and return */
83
        ldmfd   sp!, {r0-r7}    /* restore r0 thru r7 (r8 - r14 are banked) */
84
        ldmfd   sp!, {r12}
85
        msr     spsr, r12       /* restore SPSR */
86
        ldmfd   sp!, {r12,pc}^  /* restore r12 and PC, return to inst before exception occurred */
87
 
88
        .globl __ignore_abort
89
__ignore_abort:
90
        subs pc,lr,#4
91
 
92
        .globl _cspr_enable_fiq_int
93
_cspr_enable_fiq_int:
94
        mrs     r0, cpsr
95
        bic     r0, r0, #0x40
96
        msr     cpsr, r0
97
        mov     pc, lr
98
 
99
        .globl _cspr_enable_irq_int
100
_cspr_enable_irq_int:
101
        mrs     r0, cpsr
102
        bic     r0, r0, #0x80
103
        msr     cpsr, r0
104
        mov     pc, lr
105
 
106
        .bss
107
        .rept 1024
108
        .word 0
109
        .endr
110
  __irq_stack:
111
        .rept 1024
112
        .word 0
113
        .endr
114
  __fiq_stack:
115
 
116
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.