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[/] [openrisc/] [trunk/] [rtos/] [ecos-2.0/] [packages/] [hal/] [arm/] [xscale/] [iq80310/] [v2_0/] [src/] [diag/] [pci_serv.c] - Blame information for rev 174

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//=============================================================================
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//
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//      pci_serv.c - Cyclone Diagnostics
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//
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//=============================================================================
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//####ECOSGPLCOPYRIGHTBEGIN####
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// -------------------------------------------
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// This file is part of eCos, the Embedded Configurable Operating System.
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// Copyright (C) 1998, 1999, 2000, 2001, 2002, 2003 Red Hat, Inc.
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//
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// eCos is free software; you can redistribute it and/or modify it under
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// the terms of the GNU General Public License as published by the Free
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// Software Foundation; either version 2 or (at your option) any later version.
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//
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// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or
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// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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// for more details.
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//
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// You should have received a copy of the GNU General Public License along
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// with eCos; if not, write to the Free Software Foundation, Inc.,
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// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
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//
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// As a special exception, if other files instantiate templates or use macros
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// or inline functions from this file, or you compile this file and link it
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// with other works to produce a work based on this file, this file does not
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// by itself cause the resulting work to be covered by the GNU General Public
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// License. However the source code for this file must still be made available
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// in accordance with section (3) of the GNU General Public License.
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//
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// This exception does not invalidate any other reasons why a work based on
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// this file might be covered by the GNU General Public License.
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//
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// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
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// at http://sources.redhat.com/ecos/ecos-license/
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// -------------------------------------------
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//####ECOSGPLCOPYRIGHTEND####
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//=============================================================================
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//#####DESCRIPTIONBEGIN####
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//
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// Author(s):   Scott Coulter, Jeff Frazier, Eric Breeden
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// Contributors:
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// Date:        2001-01-25
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// Purpose:     
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// Description: 
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//
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//####DESCRIPTIONEND####
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//
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//===========================================================================*/
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/********************************************************************************/
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/* PCI_SERV.C - PCI driver for IQ80310                                          */
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/*                                                                              */
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/* History:                                                                     */
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/*  15sep00 ejb Ported to Cygmon on IQ80310                                     */
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/*  18dec00 snc                                                                 */
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/********************************************************************************/
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#include <redboot.h>
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#include <cyg/hal/hal_iop310.h>        // Hardware definitions
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#include "iq80310.h"
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#include "pci_bios.h"
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#undef  DEBUG_PCI
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#define IB_MA_ERROR     0x2000
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/*==========================================================================*/
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/* Globals                                                                  */
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/*==========================================================================*/
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ULONG   memspace_ptr[NUM_PCI_BUSES];
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ULONG   iospace_ptr[NUM_PCI_BUSES];
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ULONG   memspace_limit[NUM_PCI_BUSES];
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ULONG   iospace_limit[NUM_PCI_BUSES];
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UINT    nextbus;
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UINT    secondary_busno = SECONDARY_BUS_NUM;
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UINT    primary_busno = PRIMARY_BUS_NUM;
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UINT    lastbus;
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unsigned long dram_size; /* global storing the size of DRAM */
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int bus0_lastbus;        /* last secondary bus number behind bus 0 */
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int bus1_lastbus;        /* last secondary bus number behind bus 1 */
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int nmi_verbose;        /* global flag to indicate whether or not PCI Error messages should be
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                           printed.  This flag is used to prevent a painful deluge of messages
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                           when performing PCI configuration reads/writes to possibly non-existant
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                           devices. */
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int pci_config_error = FALSE; /* becomes TRUE if an NMI interrupt occurs due to a PCI config cycle */
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#define PRINT_ON()  nmi_verbose = TRUE
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#define PRINT_OFF() nmi_verbose = FALSE
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/*==========================================================================*/
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/* Function prototypes                                                      */
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/*==========================================================================*/
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typedef struct
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{
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    FUNCPTR     handler;
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    int         arg;
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    int         bus;
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    int         device;
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} INT_HANDLER;
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#define NUM_PCI_XINTS           4               /* XINT0 - XINT3 */
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#define MAX_PCI_HANDLERS        8               /* maximum handlers per PCI Xint */
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extern void hexIn(void);
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extern int pci_config_cycle;
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extern void _enableFiqIrq(void);
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extern void config_ints(void);  /* configure interrupts */
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/*********************************************************************************
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* pci_to_xint - convert a PCI device number and Interrupt line to an 80312 XINT
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*
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* This function converts a PCI slot number (0 - 7) and an Interrupt line
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* (INTA - INTD) to a i960 processor XINT number (0 - 3)
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*
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* RETURNS: OK or ERROR if arguments are invalid
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*
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*/
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STATUS pci_to_xint(int device, int intpin, int *xint)
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{
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    int device_base;    /* all devices mod 4 follow same interrupt mapping scheme */
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    /* check validity of arguments */
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    if ((intpin < INTA) || (intpin > INTD) || (device > 31))
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        return (ERROR);
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    device_base = device % 4;
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    /* interrupt mapping scheme as per PCI-to-PCI Bridge Specification */
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    switch (device_base) {
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    case 0:
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        switch (intpin) {
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        case INTA:
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            *xint = XINT0;
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            break;
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        case INTB:
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            *xint = XINT1;
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            break;
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        case INTC:
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            *xint = XINT2;
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            break;
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        case INTD:
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            *xint = XINT3;
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            break;
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        }
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        break;
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    case 1:
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        switch (intpin) {
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        case INTA:
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            *xint = XINT1;
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            break;
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        case INTB:
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            *xint = XINT2;
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            break;
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        case INTC:
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            *xint = XINT3;
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            break;
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        case INTD:
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            *xint = XINT0;
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            break;
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        }
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        break;
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    case 2:
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        switch (intpin) {
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        case INTA:
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            *xint = XINT2;
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            break;
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        case INTB:
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            *xint = XINT3;
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            break;
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        case INTC:
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            *xint = XINT0;
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            break;
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        case INTD:
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            *xint = XINT1;
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            break;
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        }
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        break;
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    case 3:
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        switch (intpin) {
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        case INTA:
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            *xint = XINT3;
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            break;
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        case INTB:
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            *xint = XINT0;
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            break;
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        case INTC:
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            *xint = XINT1;
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            break;
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        case INTD:
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            *xint = XINT2;
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            break;
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        }
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        break;
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    }
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    return (OK);
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}
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/******************************************************************************
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*
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* Checks to see if the "bus" argument identifies a PCI bus which is located
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* off of the Primary PCI bus of the board.
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*/
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int off_ppci_bus (int busno)
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{
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    if (busno == primary_busno)
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        return (TRUE);
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    else if (busno == secondary_busno)
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        return (FALSE);
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    else if (busno <= bus0_lastbus)
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        return (TRUE);
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    else
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        return (FALSE);
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}
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/******************************************************************************
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* sys_set_pci_irq - connect a PCI interrupt to a processor IRQ.
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*
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* The PCI Interrupt routing fabric on the Cyclone Hardware is not
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* reconfigurable (fixed mapping relationships) and therefore, this function
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* is not supported.
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*
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*/
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STATUS sys_set_pci_irq (int int_pin, int irq_num, int bus_dev)
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{
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    return (FUNC_NOT_SUPPORTED);
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}
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/* check if host of backplane */
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int isHost(void)
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{
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    if (*BACKPLANE_DET_REG & BP_HOST_BIT)
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        return TRUE;
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    else
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        return FALSE;
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}
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