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[/] [openrisc/] [trunk/] [rtos/] [ecos-2.0/] [packages/] [hal/] [arm/] [xscale/] [iq80321/] [v2_0/] [src/] [diag/] [pcitest.c] - Blame information for rev 174

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//=============================================================================
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//
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//      pcitest.c
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//
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//=============================================================================
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//####ECOSGPLCOPYRIGHTBEGIN####
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// -------------------------------------------
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// This file is part of eCos, the Embedded Configurable Operating System.
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// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
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//
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// eCos is free software; you can redistribute it and/or modify it under
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// the terms of the GNU General Public License as published by the Free
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// Software Foundation; either version 2 or (at your option) any later version.
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//
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// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or
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// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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// for more details.
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//
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// You should have received a copy of the GNU General Public License along
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// with eCos; if not, write to the Free Software Foundation, Inc.,
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// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
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//
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// As a special exception, if other files instantiate templates or use macros
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// or inline functions from this file, or you compile this file and link it
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// with other works to produce a work based on this file, this file does not
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// by itself cause the resulting work to be covered by the GNU General Public
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// License. However the source code for this file must still be made available
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// in accordance with section (3) of the GNU General Public License.
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//
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// This exception does not invalidate any other reasons why a work based on
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// this file might be covered by the GNU General Public License.
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//
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// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
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// at http://sources.redhat.com/ecos/ecos-license/
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// -------------------------------------------
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//####ECOSGPLCOPYRIGHTEND####
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//=============================================================================
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//#####DESCRIPTIONBEGIN####
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//
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// Author(s):   Scott Coulter, Jeff Frazier, Eric Breeden
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// Contributors: Mark Salter
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// Date:        2001-01-25
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// Purpose:     
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// Description: 
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//
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//####DESCRIPTIONEND####
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//
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//===========================================================================*/
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#include <redboot.h>
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#include <cyg/io/pci.h>
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#include "test_menu.h"
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extern int memTest (CYG_ADDRWORD startAddr, CYG_ADDRWORD endAddr);
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//
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// PCI Bus Test
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//
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// This test assumes that an IQ80310 eval board
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// is installed in the secondary PCI slot. This
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// second board must be configured with 32 Meg
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// of SDRAM minimum.
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//
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//
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void
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pci_test (MENU_ARG arg)
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{
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    cyg_pci_device dev_info;
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    cyg_pci_device_id devid;
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    cyg_uint32 mem_size;
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    cyg_uint16 cmd;
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    cyg_uint32 *start, *end;
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    int bus;
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    // First, look for iq80310 at private and public addresses
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    bus = (*ATU_PCIXSR >> 8) & 0xff;
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    if (bus == 0xff)
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        bus = 0;
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    devid = CYG_PCI_DEV_MAKE_ID(bus, CYG_PCI_DEV_MAKE_DEVFN(__SLOT_PUB, 1));
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    cyg_pci_get_device_info(devid, &dev_info);
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    if (dev_info.vendor != 0x8086 || dev_info.device != 0x530d) {
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        devid = CYG_PCI_DEV_MAKE_ID(bus, CYG_PCI_DEV_MAKE_DEVFN(__SLOT_PRIV, 1));
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        cyg_pci_get_device_info(devid, &dev_info);
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        if (dev_info.vendor != 0x8086 || dev_info.device != 0x530d) {
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            diag_printf("No iq80310 in PCI slot.\n");
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            return;
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        }
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    }
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    cyg_pci_set_memory_base(HAL_PCI_ALLOC_BASE_MEMORY + 0x2000000);
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    cyg_pci_set_io_base(HAL_PCI_ALLOC_BASE_IO);
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    cyg_pci_configure_device(&dev_info);
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    diag_printf ("iq80310 DRAM starts at PCI address %p, CPU address %p\n",
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                 dev_info.base_address[0] & CYG_PRI_CFG_BAR_MEM_MASK,
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                 dev_info.base_map[0]);
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    // enable memory space and bus master
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    cyg_pci_read_config_uint16(dev_info.devid, CYG_PCI_CFG_COMMAND, &cmd);
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    cmd |= (CYG_PCI_CFG_COMMAND_MEMORY | CYG_PCI_CFG_COMMAND_MASTER);
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    cyg_pci_write_config_uint16(dev_info.devid, CYG_PCI_CFG_COMMAND, cmd);
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    start = (cyg_uint32 *)dev_info.base_map[0];
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    // skip over 1st Mbyte of target DRAM
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    start += 0x100000/sizeof(*start);
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    // 32MB test
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    mem_size = 0x2000000 - 0x100000;
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    end = start + mem_size/sizeof(*start) - 1;
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    diag_printf("Testing memory from %p to %p.\n", start, end);
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    memTest((CYG_ADDRWORD)start, (CYG_ADDRWORD)end);
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    diag_printf ("Memory test done.\n");
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}
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