OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [rtos/] [ecos-2.0/] [packages/] [hal/] [arm/] [xscale/] [iq80321/] [v2_0/] [src/] [diag/] [pcitest.c] - Blame information for rev 565

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 27 unneback
//=============================================================================
2
//
3
//      pcitest.c
4
//
5
//=============================================================================
6
//####ECOSGPLCOPYRIGHTBEGIN####
7
// -------------------------------------------
8
// This file is part of eCos, the Embedded Configurable Operating System.
9
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
10
//
11
// eCos is free software; you can redistribute it and/or modify it under
12
// the terms of the GNU General Public License as published by the Free
13
// Software Foundation; either version 2 or (at your option) any later version.
14
//
15
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
16
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
17
// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
18
// for more details.
19
//
20
// You should have received a copy of the GNU General Public License along
21
// with eCos; if not, write to the Free Software Foundation, Inc.,
22
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
23
//
24
// As a special exception, if other files instantiate templates or use macros
25
// or inline functions from this file, or you compile this file and link it
26
// with other works to produce a work based on this file, this file does not
27
// by itself cause the resulting work to be covered by the GNU General Public
28
// License. However the source code for this file must still be made available
29
// in accordance with section (3) of the GNU General Public License.
30
//
31
// This exception does not invalidate any other reasons why a work based on
32
// this file might be covered by the GNU General Public License.
33
//
34
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
35
// at http://sources.redhat.com/ecos/ecos-license/
36
// -------------------------------------------
37
//####ECOSGPLCOPYRIGHTEND####
38
//=============================================================================
39
//#####DESCRIPTIONBEGIN####
40
//
41
// Author(s):   Scott Coulter, Jeff Frazier, Eric Breeden
42
// Contributors: Mark Salter
43
// Date:        2001-01-25
44
// Purpose:     
45
// Description: 
46
//
47
//####DESCRIPTIONEND####
48
//
49
//===========================================================================*/
50
 
51
#include <redboot.h>
52
#include <cyg/io/pci.h>
53
#include "test_menu.h"
54
 
55
extern int memTest (CYG_ADDRWORD startAddr, CYG_ADDRWORD endAddr);
56
 
57
//
58
// PCI Bus Test
59
//
60
// This test assumes that an IQ80310 eval board
61
// is installed in the secondary PCI slot. This
62
// second board must be configured with 32 Meg
63
// of SDRAM minimum.
64
//
65
//
66
void
67
pci_test (MENU_ARG arg)
68
{
69
    cyg_pci_device dev_info;
70
    cyg_pci_device_id devid;
71
    cyg_uint32 mem_size;
72
    cyg_uint16 cmd;
73
    cyg_uint32 *start, *end;
74
    int bus;
75
 
76
    // First, look for iq80310 at private and public addresses
77
 
78
    bus = (*ATU_PCIXSR >> 8) & 0xff;
79
    if (bus == 0xff)
80
        bus = 0;
81
 
82
    devid = CYG_PCI_DEV_MAKE_ID(bus, CYG_PCI_DEV_MAKE_DEVFN(__SLOT_PUB, 1));
83
    cyg_pci_get_device_info(devid, &dev_info);
84
 
85
    if (dev_info.vendor != 0x8086 || dev_info.device != 0x530d) {
86
        devid = CYG_PCI_DEV_MAKE_ID(bus, CYG_PCI_DEV_MAKE_DEVFN(__SLOT_PRIV, 1));
87
        cyg_pci_get_device_info(devid, &dev_info);
88
 
89
        if (dev_info.vendor != 0x8086 || dev_info.device != 0x530d) {
90
            diag_printf("No iq80310 in PCI slot.\n");
91
            return;
92
        }
93
    }
94
 
95
    cyg_pci_set_memory_base(HAL_PCI_ALLOC_BASE_MEMORY + 0x2000000);
96
    cyg_pci_set_io_base(HAL_PCI_ALLOC_BASE_IO);
97
 
98
    cyg_pci_configure_device(&dev_info);
99
 
100
    diag_printf ("iq80310 DRAM starts at PCI address %p, CPU address %p\n",
101
                 dev_info.base_address[0] & CYG_PRI_CFG_BAR_MEM_MASK,
102
                 dev_info.base_map[0]);
103
 
104
    // enable memory space and bus master
105
    cyg_pci_read_config_uint16(dev_info.devid, CYG_PCI_CFG_COMMAND, &cmd);
106
    cmd |= (CYG_PCI_CFG_COMMAND_MEMORY | CYG_PCI_CFG_COMMAND_MASTER);
107
    cyg_pci_write_config_uint16(dev_info.devid, CYG_PCI_CFG_COMMAND, cmd);
108
 
109
    start = (cyg_uint32 *)dev_info.base_map[0];
110
    // skip over 1st Mbyte of target DRAM
111
    start += 0x100000/sizeof(*start);
112
    // 32MB test
113
    mem_size = 0x2000000 - 0x100000;
114
    end = start + mem_size/sizeof(*start) - 1;
115
 
116
    diag_printf("Testing memory from %p to %p.\n", start, end);
117
 
118
    memTest((CYG_ADDRWORD)start, (CYG_ADDRWORD)end);
119
 
120
    diag_printf ("Memory test done.\n");
121
}
122
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.