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//==========================================================================

//

//      iq80321_misc.c

//

//      HAL misc board support code for Intel XScale IQ80321

//

//==========================================================================

//####ECOSGPLCOPYRIGHTBEGIN####

// -------------------------------------------

// This file is part of eCos, the Embedded Configurable Operating System.

// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.

//

// eCos is free software; you can redistribute it and/or modify it under

// the terms of the GNU General Public License as published by the Free

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// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.

//

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// or inline functions from this file, or you compile this file and link it

// with other works to produce a work based on this file, this file does not

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//####ECOSGPLCOPYRIGHTEND####

//==========================================================================

//#####DESCRIPTIONBEGIN####

//

// Author(s):    msalter

// Contributors: msalter

// Date:         2001-12-03

// Purpose:      HAL board support

// Description:  Implementations of HAL board interfaces

//

//####DESCRIPTIONEND####

//

//========================================================================*/

#include <pkgconf/hal.h>

#include <pkgconf/system.h>

#include CYGBLD_HAL_PLATFORM_H

#include <cyg/infra/cyg_type.h>         // base types

#include <cyg/infra/cyg_trac.h>         // tracing macros

#include <cyg/infra/cyg_ass.h>          // assertion macros

#include <cyg/hal/hal_io.h>             // IO macros

#include <cyg/hal/hal_arch.h>           // Register state info

#include <cyg/hal/hal_diag.h>

#include <cyg/hal/hal_intr.h>           // Interrupt names

#include <cyg/hal/hal_cache.h>

#include <cyg/hal/hal_verde.h>          // Hardware definitions

#include <cyg/hal/iq80321.h>            // Platform specifics

#include <cyg/infra/diag.h>             // diag_printf

#ifdef CYGPKG_IO_PCI

cyg_uint32 cyg_pci_window_real_base = 0;

#endif

//

// Platform specific initialization

//

void

plf_hardware_init(void)

{

    INTCTL_WRITE(0);  // mask all irqs

    INTSTR_WRITE(0);  // everything goes to IRQ

    *PIRSR = 0x0f;

// RAM startup only - rewrite relevent bits depending on config

#ifndef CYG_HAL_STARTUP_ROM

    HAL_DCACHE_SYNC();            // Force data out

    HAL_DCACHE_INVALIDATE_ALL();  // Flush TLBs: make new mmu state effective

#endif // ! CYG_HAL_STARTUP_ROM - RAM start only

}

//

// Memory layout - runtime variations of all kinds.

//

externC cyg_uint8 *

hal_arm_mem_real_region_top( cyg_uint8 *regionend )

{

    CYG_ASSERT( hal_dram_size > 0, "Didn't detect DRAM size!" );

    CYG_ASSERT( hal_dram_size <=  256<<20,

                "More than 256MB reported - that can't be right" );

    CYG_ASSERT( 0 == (hal_dram_size & 0xfffff),

                "hal_dram_size not whole Mb" );

    // is it the "normal" end of the DRAM region? If so, it should be

    // replaced by the real size

    if ( regionend ==

         ((cyg_uint8 *)CYGMEM_REGION_ram + CYGMEM_REGION_ram_SIZE) ) {

        regionend = (cyg_uint8 *)CYGMEM_REGION_ram + hal_dram_size;

    }

    // Also, we must check for the top of the heap having moved.  This is

    // because the heap does not abut the top of memory.

#ifdef CYGMEM_SECTION_heap1

    if ( regionend ==

         ((cyg_uint8 *)CYGMEM_SECTION_heap1 + CYGMEM_SECTION_heap1_SIZE) ) {

        // hal_dram_size excludes the PCI window on this platform.

        if ( regionend > (cyg_uint8 *)CYGMEM_REGION_ram + hal_dram_size )

            regionend = (cyg_uint8 *)CYGMEM_REGION_ram + hal_dram_size;

    }

#endif

    return regionend;

}

// ------------------------------------------------------------------------

// EOF iq80321_misc.c