| 1 |
27 |
unneback |
/*=============================================================================
|
| 2 |
|
|
//
|
| 3 |
|
|
// hal_platform_setup.h
|
| 4 |
|
|
//
|
| 5 |
|
|
// Platform specific support for HAL (assembly code)
|
| 6 |
|
|
//
|
| 7 |
|
|
//==========================================================================
|
| 8 |
|
|
//####ECOSGPLCOPYRIGHTBEGIN####
|
| 9 |
|
|
// -------------------------------------------
|
| 10 |
|
|
// This file is part of eCos, the Embedded Configurable Operating System.
|
| 11 |
|
|
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
|
| 12 |
|
|
//
|
| 13 |
|
|
// eCos is free software; you can redistribute it and/or modify it under
|
| 14 |
|
|
// the terms of the GNU General Public License as published by the Free
|
| 15 |
|
|
// Software Foundation; either version 2 or (at your option) any later version.
|
| 16 |
|
|
//
|
| 17 |
|
|
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
|
| 18 |
|
|
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
| 19 |
|
|
// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
|
| 20 |
|
|
// for more details.
|
| 21 |
|
|
//
|
| 22 |
|
|
// You should have received a copy of the GNU General Public License along
|
| 23 |
|
|
// with eCos; if not, write to the Free Software Foundation, Inc.,
|
| 24 |
|
|
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
|
| 25 |
|
|
//
|
| 26 |
|
|
// As a special exception, if other files instantiate templates or use macros
|
| 27 |
|
|
// or inline functions from this file, or you compile this file and link it
|
| 28 |
|
|
// with other works to produce a work based on this file, this file does not
|
| 29 |
|
|
// by itself cause the resulting work to be covered by the GNU General Public
|
| 30 |
|
|
// License. However the source code for this file must still be made available
|
| 31 |
|
|
// in accordance with section (3) of the GNU General Public License.
|
| 32 |
|
|
//
|
| 33 |
|
|
// This exception does not invalidate any other reasons why a work based on
|
| 34 |
|
|
// this file might be covered by the GNU General Public License.
|
| 35 |
|
|
//
|
| 36 |
|
|
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
|
| 37 |
|
|
// at http://sources.redhat.com/ecos/ecos-license/
|
| 38 |
|
|
// -------------------------------------------
|
| 39 |
|
|
//####ECOSGPLCOPYRIGHTEND####
|
| 40 |
|
|
//==========================================================================
|
| 41 |
|
|
//#####DESCRIPTIONBEGIN####
|
| 42 |
|
|
//
|
| 43 |
|
|
// Author(s): <knud.woehler@microplex.de>
|
| 44 |
|
|
// Date: 2003-01-09
|
| 45 |
|
|
//
|
| 46 |
|
|
//####DESCRIPTIONEND####
|
| 47 |
|
|
//
|
| 48 |
|
|
//===========================================================================*/
|
| 49 |
|
|
#ifndef CYGONCE_HAL_PLATFORM_SETUP_H
|
| 50 |
|
|
#define CYGONCE_HAL_PLATFORM_SETUP_H
|
| 51 |
|
|
|
| 52 |
|
|
#include <pkgconf/system.h> // System-wide configuration info
|
| 53 |
|
|
#include CYGBLD_HAL_VARIANT_H // Variant specific configuration
|
| 54 |
|
|
#include CYGBLD_HAL_PLATFORM_H // Platform specific configuration
|
| 55 |
|
|
#include <cyg/hal/hal_pxa2x0.h> // Platform specific hardware definitions
|
| 56 |
|
|
#include <cyg/hal/hal_mmu.h> // MMU definitions
|
| 57 |
|
|
#include <cyg/hal/hal_mm.h> // more MMU definitions
|
| 58 |
|
|
#include <cyg/hal/mpc50.h>
|
| 59 |
|
|
|
| 60 |
|
|
/**********************************************************************************************************************
|
| 61 |
|
|
* MMU/Cache
|
| 62 |
|
|
**********************************************************************************************************************/
|
| 63 |
|
|
.macro init_mmu_cache_on
|
| 64 |
|
|
ldr r0, =0x2001
|
| 65 |
|
|
mcr p15, 0, r0, c15, c1, 0
|
| 66 |
|
|
mcr p15, 0, r0, c7, c10, 4 // drain the write & fill buffers
|
| 67 |
|
|
CPWAIT r0
|
| 68 |
|
|
mcr p15, 0, r0, c7, c7, 0 // flush Icache, Dcache and BTB
|
| 69 |
|
|
CPWAIT r0
|
| 70 |
|
|
mcr p15, 0, r0, c8, c7, 0 // flush instuction and data TLBs
|
| 71 |
|
|
CPWAIT r0
|
| 72 |
|
|
|
| 73 |
|
|
// Icache on
|
| 74 |
|
|
mrc p15, 0, r0, c1, c0, 0
|
| 75 |
|
|
orr r0, r0, #MMU_Control_I
|
| 76 |
|
|
orr r0, r0, #MMU_Control_BTB // Enable the BTB
|
| 77 |
|
|
mcr p15, 0, r0, c1, c0, 0
|
| 78 |
|
|
CPWAIT r0
|
| 79 |
|
|
|
| 80 |
|
|
// create stack for "C"
|
| 81 |
|
|
ldr r1,=__startup_stack
|
| 82 |
|
|
ldr r2,=PXA2X0_RAM_BANK0_BASE
|
| 83 |
|
|
orr sp,r1,r2
|
| 84 |
|
|
bl hal_mmu_init // create MMU Tables
|
| 85 |
|
|
|
| 86 |
|
|
// Enable permission checks in all domains
|
| 87 |
|
|
ldr r0, =0x55555555
|
| 88 |
|
|
mcr p15, 0, r0, c3, c0, 0
|
| 89 |
|
|
|
| 90 |
|
|
// MMU on
|
| 91 |
|
|
ldr r2,=1f
|
| 92 |
|
|
mrc p15, 0, r0, c1, c0, 0
|
| 93 |
|
|
orr r0, r0, #MMU_Control_M
|
| 94 |
|
|
orr r0, r0, #MMU_Control_R
|
| 95 |
|
|
mcr p15, 0, r0, c1, c0, 0
|
| 96 |
|
|
mov pc,r2
|
| 97 |
|
|
nop
|
| 98 |
|
|
nop
|
| 99 |
|
|
nop
|
| 100 |
|
|
1:
|
| 101 |
|
|
|
| 102 |
|
|
mcr p15, 0, r0, c7, c10, 4 // drain the write & fill buffers
|
| 103 |
|
|
CPWAIT r0
|
| 104 |
|
|
|
| 105 |
|
|
// Dcache on
|
| 106 |
|
|
mrc p15, 0, r0, c1, c0, 0
|
| 107 |
|
|
orr r0, r0, #MMU_Control_C
|
| 108 |
|
|
mcr p15, 0, r0, c1, c0, 0
|
| 109 |
|
|
CPWAIT r0
|
| 110 |
|
|
|
| 111 |
|
|
// clean/drain/flush the main Dcache
|
| 112 |
|
|
mov r1, #0xc0000000
|
| 113 |
|
|
mov r0, #1024
|
| 114 |
|
|
2:
|
| 115 |
|
|
mcr p15, 0, r1, c7, c2, 5
|
| 116 |
|
|
add r1, r1, #32
|
| 117 |
|
|
subs r0, r0, #1
|
| 118 |
|
|
bne 2b
|
| 119 |
|
|
|
| 120 |
|
|
// clean/drain/flush the mini Dcache
|
| 121 |
|
|
//ldr r1, =(DCACHE_FLUSH_AREA+DCACHE_SIZE) // use a CACHEABLE area of
|
| 122 |
|
|
mov r0, #64 // number of lines in the mini Dcache
|
| 123 |
|
|
3:
|
| 124 |
|
|
mcr p15, 0, r1, c7, c2, 5 // allocate a Dcache line
|
| 125 |
|
|
add r1, r1, #32 // increment the address to
|
| 126 |
|
|
subs r0, r0, #1 // decrement the loop count
|
| 127 |
|
|
bne 3b
|
| 128 |
|
|
|
| 129 |
|
|
// flush Dcache
|
| 130 |
|
|
mcr p15, 0, r0, c7, c6, 0
|
| 131 |
|
|
CPWAIT r0
|
| 132 |
|
|
|
| 133 |
|
|
// drain the write & fill buffers
|
| 134 |
|
|
mcr p15, 0, r0, c7, c10, 4
|
| 135 |
|
|
CPWAIT r0
|
| 136 |
|
|
|
| 137 |
|
|
.endm
|
| 138 |
|
|
|
| 139 |
|
|
|
| 140 |
|
|
|
| 141 |
|
|
.macro init_mmu_off
|
| 142 |
|
|
mov r0, #0x78
|
| 143 |
|
|
mcr p15, 0, r0, c1, c0, 0 // caches off -- MMU off or ID map
|
| 144 |
|
|
mcr p15, 0, r0, c7, c7, 0 // Invalidate the I & D cache, mini- d cache, and BTB
|
| 145 |
|
|
mcr p15, 0, r0, c7, c10, 4 // Drain write buffer -- r0 ignored
|
| 146 |
|
|
CPWAIT r0
|
| 147 |
|
|
nop
|
| 148 |
|
|
nop
|
| 149 |
|
|
nop
|
| 150 |
|
|
nop
|
| 151 |
|
|
mvn r0, #0
|
| 152 |
|
|
mcr p15, 0, r0, c3, c0, 0
|
| 153 |
|
|
.endm
|
| 154 |
|
|
|
| 155 |
|
|
/**********************************************************************************************************************
|
| 156 |
|
|
* Clock
|
| 157 |
|
|
**********************************************************************************************************************/
|
| 158 |
|
|
#define CCCR_OFFS (PXA2X0_CCCR-PXA2X0_CLK_BASE)
|
| 159 |
|
|
.macro init_clks
|
| 160 |
|
|
ldr r1, =PXA2X0_CLK_BASE
|
| 161 |
|
|
// TurboMode=400MHz/RunMode=200MHz/Memory=100MHz/SDRam=100MHz
|
| 162 |
|
|
// ldr r0, =(PXA2X0_CCCR_L27 | PXA2X0_CCCR_M2 | PXA2X0_CCCR_N20)
|
| 163 |
|
|
// TurboMode=300MHz/RunMode=200MHz/Memory=100MHz/SDRam=100MHz
|
| 164 |
|
|
// ldr r0, =(PXA2X0_CCCR_L27 | PXA2X0_CCCR_M2 | PXA2X0_CCCR_N15)
|
| 165 |
|
|
adr r0, mpc50_static_info
|
| 166 |
|
|
ldr r0, [r0, #MPC50_VAL_OFFS_CCCR]
|
| 167 |
|
|
|
| 168 |
|
|
str r0, [r1, #CCCR_OFFS] // set Core Clock
|
| 169 |
|
|
mov r0, #3
|
| 170 |
|
|
mcr p14, 0, r0, c6, c0, 0 // Turbo Mode on
|
| 171 |
|
|
.endm
|
| 172 |
|
|
|
| 173 |
|
|
/**********************************************************************************************************************
|
| 174 |
|
|
* Interrupt controller
|
| 175 |
|
|
**********************************************************************************************************************/
|
| 176 |
|
|
#define ICLR_OFFS (PXA2X0_ICLR-PXA2X0_IC_BASE)
|
| 177 |
|
|
#define ICMR_OFFS (PXA2X0_ICMR-PXA2X0_IC_BASE)
|
| 178 |
|
|
.macro init_intc_cnt
|
| 179 |
|
|
ldr r1, =PXA2X0_IC_BASE
|
| 180 |
|
|
mov r0, #0
|
| 181 |
|
|
str r0, [r1, #ICLR_OFFS] // clear Interrupt level Register
|
| 182 |
|
|
str r0, [r1, #ICMR_OFFS] // clear Interrupt mask Register
|
| 183 |
|
|
.endm
|
| 184 |
|
|
|
| 185 |
|
|
/**********************************************************************************************************************
|
| 186 |
|
|
* SDRAM
|
| 187 |
|
|
**********************************************************************************************************************/
|
| 188 |
|
|
|
| 189 |
|
|
//#define MDCNFG_VAL 0x094B094B // SDRAM Config Reg (32Bit, 9 Col, 13 Row, 2 Bank, CL2)
|
| 190 |
|
|
//#define MDREFR_VAL 0x0005b018 // SDRAM Refresh Reg SDCLK=memory clock
|
| 191 |
|
|
//#define MDREFR_VAL 0x000ff018 // SDRAM Refresh Reg SDCLK=1/2 memory clock
|
| 192 |
|
|
#define MDMRS_VAL 0x00000000 // SDRAM Mode Reg Set Config Reg
|
| 193 |
|
|
#define MSC0_VAL 0x199123da // CS1(FPGA)/CS0(Flash)
|
| 194 |
|
|
#define MSC1_VAL 0x7ff07ff1 // CS3(not used)/CS2(ETH)
|
| 195 |
|
|
|
| 196 |
|
|
#define OSCR_OFFS (PXA2X0_OSCR-PXA2X0_OSTIMER_BASE)
|
| 197 |
|
|
#define MDREFR_OFFS (PXA2X0_MDREFR-PXA2X0_MEMORY_CTL_BASE)
|
| 198 |
|
|
#define MDCNFG_OFFS (PXA2X0_MDCNFG-PXA2X0_MEMORY_CTL_BASE)
|
| 199 |
|
|
#define MDMRS_OFFS (PXA2X0_MDMRS-PXA2X0_MEMORY_CTL_BASE)
|
| 200 |
|
|
#define MSC0_OFFS (PXA2X0_MSC0-PXA2X0_MEMORY_CTL_BASE)
|
| 201 |
|
|
#define MSC1_OFFS (PXA2X0_MSC1-PXA2X0_MEMORY_CTL_BASE)
|
| 202 |
|
|
#define MSC2_OFFS (PXA2X0_MSC2-PXA2X0_MEMORY_CTL_BASE)
|
| 203 |
|
|
.macro init_sdram_cnt
|
| 204 |
|
|
// Hardware Reset Operation (S. 5-83)
|
| 205 |
|
|
// Step 1
|
| 206 |
|
|
|
| 207 |
|
|
// wait 200 usec
|
| 208 |
|
|
ldr r1, =PXA2X0_OSTIMER_BASE // set OS Timer Count
|
| 209 |
|
|
mov r0, #0
|
| 210 |
|
|
str r0, [r1, #OSCR_OFFS]
|
| 211 |
|
|
ldr r2, =0x300 // wait 200 usec
|
| 212 |
|
|
61:
|
| 213 |
|
|
ldr r0, [r1, #OSCR_OFFS]
|
| 214 |
|
|
cmp r2, r0
|
| 215 |
|
|
bgt 61b
|
| 216 |
|
|
|
| 217 |
|
|
ldr r1, =PXA2X0_MEMORY_CTL_BASE
|
| 218 |
|
|
|
| 219 |
|
|
ldr r0, =MSC0_VAL
|
| 220 |
|
|
str r0, [r1, #MSC0_OFFS] // FPGA/Flash
|
| 221 |
|
|
|
| 222 |
|
|
ldr r0, =MSC1_VAL
|
| 223 |
|
|
str r0, [r1, #MSC1_OFFS] // ETH
|
| 224 |
|
|
|
| 225 |
|
|
// Refresh Register
|
| 226 |
|
|
//ldr r3, =MDREFR_VAL // load SDRAM refresh info
|
| 227 |
|
|
adr r3, mpc50_static_info
|
| 228 |
|
|
ldr r3, [r3, #MPC50_VAL_OFFS_MDREFR]
|
| 229 |
|
|
|
| 230 |
|
|
|
| 231 |
|
|
ldr r2, =0xFFF // DRI field
|
| 232 |
|
|
and r3, r3, r2
|
| 233 |
|
|
ldr r4, [r1, #MDREFR_OFFS] // read Reset Status
|
| 234 |
|
|
bic r4, r4, r2
|
| 235 |
|
|
bic r4, r4, #(0x01000000 | 0x02000000) // clear K1Free, K2Free,
|
| 236 |
|
|
bic r4, r4, #0x00004000 // K0DB2
|
| 237 |
|
|
orr r4, r4, r3 // add DRI field
|
| 238 |
|
|
str r4, [r1, #MDREFR_OFFS] //
|
| 239 |
|
|
ldr r4, [r1, #MDREFR_OFFS]
|
| 240 |
|
|
|
| 241 |
|
|
// Step 2
|
| 242 |
|
|
//
|
| 243 |
|
|
|
| 244 |
|
|
// Step 3
|
| 245 |
|
|
//ldr r3, =MDREFR_VAL // load SDRAM Refresh Info
|
| 246 |
|
|
adr r3, mpc50_static_info
|
| 247 |
|
|
ldr r3, [r3, #MPC50_VAL_OFFS_MDREFR]
|
| 248 |
|
|
|
| 249 |
|
|
|
| 250 |
|
|
ldr r2, =0x000f0000
|
| 251 |
|
|
and r3, r3, r2
|
| 252 |
|
|
orr r4, r4, r3
|
| 253 |
|
|
str r4, [r1, #MDREFR_OFFS]
|
| 254 |
|
|
ldr r4, [r1, #MDREFR_OFFS]
|
| 255 |
|
|
|
| 256 |
|
|
bic r4, r4, #0x00400000 // Self Refresh off
|
| 257 |
|
|
str r4, [r1, #MDREFR_OFFS]
|
| 258 |
|
|
ldr r4, [r1, #MDREFR_OFFS]
|
| 259 |
|
|
|
| 260 |
|
|
orr r4, r4, #0x00008000 // SDCKE1 on
|
| 261 |
|
|
str r4, [r1, #MDREFR_OFFS]
|
| 262 |
|
|
ldr r4, [r1, #MDREFR_OFFS]
|
| 263 |
|
|
|
| 264 |
|
|
orr r4, r4, #0x00800000 // K0Free on
|
| 265 |
|
|
str r4, [r1, #MDREFR_OFFS]
|
| 266 |
|
|
ldr r4, [r1, #MDREFR_OFFS]
|
| 267 |
|
|
nop
|
| 268 |
|
|
nop
|
| 269 |
|
|
|
| 270 |
|
|
// Step 4
|
| 271 |
|
|
//ldr r2, =MDCNFG_VAL
|
| 272 |
|
|
adr r2, mpc50_static_info
|
| 273 |
|
|
ldr r2, [r2, #MPC50_VAL_OFFS_MDCNFG]
|
| 274 |
|
|
|
| 275 |
|
|
|
| 276 |
|
|
bic r2, r2, #0x0003 // DE1-0
|
| 277 |
|
|
bic r2, r2, #0x00030000 // DE3-2
|
| 278 |
|
|
str r2, [r1, #MDCNFG_OFFS]
|
| 279 |
|
|
|
| 280 |
|
|
// Step 5
|
| 281 |
|
|
// wait 200 usec
|
| 282 |
|
|
ldr r1, =PXA2X0_OSTIMER_BASE
|
| 283 |
|
|
mov r0, #0
|
| 284 |
|
|
str r0, [r1, #OSCR_OFFS]
|
| 285 |
|
|
ldr r2, =0x300
|
| 286 |
|
|
71:
|
| 287 |
|
|
ldr r0, [r1, #OSCR_OFFS]
|
| 288 |
|
|
cmp r2, r0
|
| 289 |
|
|
bgt 71b
|
| 290 |
|
|
|
| 291 |
|
|
// Step 6
|
| 292 |
|
|
mov r0, #0x78
|
| 293 |
|
|
mcr p15, 0, r0, c1, c0, 0 // (caches off, MMU off, etc.)
|
| 294 |
|
|
|
| 295 |
|
|
// Step 7
|
| 296 |
|
|
ldr r2, =PXA2X0_RAM_BANK0_BASE
|
| 297 |
|
|
str r2, [r2]
|
| 298 |
|
|
str r2, [r2]
|
| 299 |
|
|
str r2, [r2]
|
| 300 |
|
|
str r2, [r2]
|
| 301 |
|
|
str r2, [r2]
|
| 302 |
|
|
str r2, [r2]
|
| 303 |
|
|
str r2, [r2]
|
| 304 |
|
|
str r2, [r2]
|
| 305 |
|
|
|
| 306 |
|
|
// Step 8
|
| 307 |
|
|
//
|
| 308 |
|
|
// Step 9
|
| 309 |
|
|
// SDRAM enable
|
| 310 |
|
|
//ldr r3, =MDCNFG_VAL
|
| 311 |
|
|
adr r3, mpc50_static_info
|
| 312 |
|
|
ldr r3, [r3, #MPC50_VAL_OFFS_MDCNFG]
|
| 313 |
|
|
|
| 314 |
|
|
|
| 315 |
|
|
ldr r2, =0x00030003
|
| 316 |
|
|
and r2, r3, r2
|
| 317 |
|
|
ldr r1, =PXA2X0_MEMORY_CTL_BASE
|
| 318 |
|
|
ldr r3, [r1, #MDCNFG_OFFS]
|
| 319 |
|
|
orr r3, r3, r2
|
| 320 |
|
|
str r3, [r1, #MDCNFG_OFFS]
|
| 321 |
|
|
|
| 322 |
|
|
// Step 10
|
| 323 |
|
|
ldr r2, =MDMRS_VAL
|
| 324 |
|
|
str r2, [r1, #MDMRS_OFFS]
|
| 325 |
|
|
.endm
|
| 326 |
|
|
|
| 327 |
|
|
|
| 328 |
|
|
/**********************************************************************************************************************
|
| 329 |
|
|
* GPIOs
|
| 330 |
|
|
**********************************************************************************************************************/
|
| 331 |
|
|
|
| 332 |
|
|
// GPIO Name Pin GPDR GAFR GPSR
|
| 333 |
|
|
|
| 334 |
|
|
// 0 INT0 L10 0 00 0
|
| 335 |
|
|
// 1 INT1 L12 0 00 0
|
| 336 |
|
|
// 2 FLX-CLK L13 1 00 0
|
| 337 |
|
|
// 3 FLX-DAT K14 1 00 0
|
| 338 |
|
|
|
| 339 |
|
|
// 4 FLX-CONFIG J12 1 00 1
|
| 340 |
|
|
// 5 FLX-STATUS J11 0 00 0
|
| 341 |
|
|
// 6 FLX-CONFDONE H14 0 00 0
|
| 342 |
|
|
// 7 LAN_INT G15 0 00 0
|
| 343 |
|
|
|
| 344 |
|
|
// 8 USB-H-ON F14 1 00 1
|
| 345 |
|
|
// 9 USB-CL-ON F12 0 00 0
|
| 346 |
|
|
// 10 MPSB-INT0 F7 0 00 0
|
| 347 |
|
|
// 11 - A7 0 00 0
|
| 348 |
|
|
|
| 349 |
|
|
// 12 MPSB-INT1 B6 0 00 0
|
| 350 |
|
|
// 13 MBGNT B5 1 10 0
|
| 351 |
|
|
// 14 MBREQ B4 0 01 0
|
| 352 |
|
|
// 15 nCS_1 T8 1 10 1
|
| 353 |
|
|
|
| 354 |
|
|
#define GAFR0_L_VAL 0x80000000 //0x98000000
|
| 355 |
|
|
|
| 356 |
|
|
// 16 PWM0 E12 0 00 0
|
| 357 |
|
|
// 17 PWM1 D12 0 00 0
|
| 358 |
|
|
// 18 RDY C1 0 01 0
|
| 359 |
|
|
// 19 DREQ[1] N14 0 00 0
|
| 360 |
|
|
|
| 361 |
|
|
// 20 DREQ[0] N12 0 00 0
|
| 362 |
|
|
// 21 DVAL0 N15 0 00 0
|
| 363 |
|
|
// 22 DVAL1 M12 0 00 0
|
| 364 |
|
|
// 23 SSPSCLK F9 0 00 0
|
| 365 |
|
|
|
| 366 |
|
|
// 24 SSPSFRM E9 0 00 0
|
| 367 |
|
|
// 25 SSPTXD D9 0 00 0
|
| 368 |
|
|
// 26 SSPRXD A9 0 00 0
|
| 369 |
|
|
// 27 SSPEXTCLK B9 0 00 0
|
| 370 |
|
|
|
| 371 |
|
|
// 28 BITCLK C9 0 00 0
|
| 372 |
|
|
// 29 SDATIN0 E10 0 00 0
|
| 373 |
|
|
// 30 SDATOUT A10 0 00 0
|
| 374 |
|
|
// 31 SYNC E11 0 00 0
|
| 375 |
|
|
|
| 376 |
|
|
#define GPDR0_VAL 0x0000811c //0x0000a11c
|
| 377 |
|
|
#define GAFR0_U_VAL 0x00000010
|
| 378 |
|
|
#define GPSR0_VAL 0x00008110
|
| 379 |
|
|
|
| 380 |
|
|
// 32 SDATIN1 A16 0 00 0
|
| 381 |
|
|
// 33 Reset-Button T13 0 00 0
|
| 382 |
|
|
// 34 FFRXD A13 0 01 0
|
| 383 |
|
|
// 35 FFCTS A14 0 01 0
|
| 384 |
|
|
|
| 385 |
|
|
// 36 FFDCD A12 0 01 0
|
| 386 |
|
|
// 37 FFDSR B11 0 01 0
|
| 387 |
|
|
// 38 FFRI B10 0 01 0
|
| 388 |
|
|
// 39 FFTXD E13 1 10 1
|
| 389 |
|
|
|
| 390 |
|
|
// 40 FFDTR F10 1 10 1
|
| 391 |
|
|
// 41 FFRTS F8 1 10 1
|
| 392 |
|
|
// 42 BTRXD B13 0 00 0
|
| 393 |
|
|
// 43 BTTXD D13 0 00 0
|
| 394 |
|
|
|
| 395 |
|
|
// 44 BTCTS A15 0 00 0
|
| 396 |
|
|
// 45 BTRTS B14 0 00 0
|
| 397 |
|
|
// 46 IRRXD B15 0 00 0
|
| 398 |
|
|
// 47 IRTXD C15 0 00 0
|
| 399 |
|
|
|
| 400 |
|
|
#define GAFR1_L_VAL 0x000a9550
|
| 401 |
|
|
|
| 402 |
|
|
|
| 403 |
|
|
// 48 LED_DP P13 1 00 0
|
| 404 |
|
|
// 49 LED_G T14 1 00 0
|
| 405 |
|
|
// 50 LED_F T15 1 00 0
|
| 406 |
|
|
// 51 LED_E R15 1 00 0
|
| 407 |
|
|
|
| 408 |
|
|
// 52 LED_D P14 1 00 0
|
| 409 |
|
|
// 53 LED_C R16 1 00 0
|
| 410 |
|
|
// 54 LED_B P16 1 00 0
|
| 411 |
|
|
// 55 LED_A M13 1 00 0
|
| 412 |
|
|
|
| 413 |
|
|
// 56 GPIO56 N16 0 00 0
|
| 414 |
|
|
// 57 GPIO57 M16 0 00 0
|
| 415 |
|
|
// 58 LCDD0 E7 0 00 0
|
| 416 |
|
|
// 59 LCDD1 D7 0 00 0
|
| 417 |
|
|
|
| 418 |
|
|
// 60 LCDD2 C7 0 00 0
|
| 419 |
|
|
// 61 LCDD3 B7 0 00 0
|
| 420 |
|
|
// 62 LCDD4 E6 0 00 0
|
| 421 |
|
|
// 63 LCDD5 D6 0 00 0
|
| 422 |
|
|
|
| 423 |
|
|
#define GPDR1_VAL 0x00ff0380
|
| 424 |
|
|
#define GAFR1_U_VAL 0x00000000
|
| 425 |
|
|
#define GPSR1_VAL 0x00000380
|
| 426 |
|
|
#define GPSR_LED_VAL 0x00ff0000
|
| 427 |
|
|
|
| 428 |
|
|
// 64 LCDD6 E5 0 00 0
|
| 429 |
|
|
// 65 LCDD7 A6 0 00 0
|
| 430 |
|
|
// 66 LCDD8 C5 0 00 0
|
| 431 |
|
|
// 67 LCDD9 A5 0 00 0
|
| 432 |
|
|
|
| 433 |
|
|
// 68 LCDD10 D5 0 00 0
|
| 434 |
|
|
// 69 LCDD11 A4 0 00 0
|
| 435 |
|
|
// 70 LCDD12 A3 0 00 0
|
| 436 |
|
|
// 71 LCDD13 A2 0 00 0
|
| 437 |
|
|
|
| 438 |
|
|
// 72 LCDD14 C3 0 00 0
|
| 439 |
|
|
// 73 LCDD15 B3 0 00 0
|
| 440 |
|
|
// 74 LCDFCLK E8 0 00 0
|
| 441 |
|
|
// 75 LCDLCLK D8 0 00 0
|
| 442 |
|
|
|
| 443 |
|
|
// 76 LCDPCLK B8 0 00 0
|
| 444 |
|
|
// 77 LCDBIAS A8 0 00 0
|
| 445 |
|
|
// 78 n_CS2 P9 1 10 1
|
| 446 |
|
|
// 79 LAN_RES T9 1 00 1
|
| 447 |
|
|
|
| 448 |
|
|
#define GAFR2_L_VAL 0x20000000
|
| 449 |
|
|
|
| 450 |
|
|
// 80 n_CS4 R13 0 00 0
|
| 451 |
|
|
|
| 452 |
|
|
#define GPDR2_VAL 0x0000c000
|
| 453 |
|
|
#define GAFR2_U_VAL 0x00000000
|
| 454 |
|
|
#define GPSR2_VAL 0x0000c000
|
| 455 |
|
|
|
| 456 |
|
|
|
| 457 |
|
|
#define GPSR0_OFFS (PXA2X0_GPSR0-PXA2X0_GPIO_BASE)
|
| 458 |
|
|
#define GPCR0_OFFS (PXA2X0_GPCR0-PXA2X0_GPIO_BASE)
|
| 459 |
|
|
#define GPSR1_OFFS (PXA2X0_GPSR1-PXA2X0_GPIO_BASE)
|
| 460 |
|
|
#define GPCR1_OFFS (PXA2X0_GPCR1-PXA2X0_GPIO_BASE)
|
| 461 |
|
|
#define GPSR2_OFFS (PXA2X0_GPSR2-PXA2X0_GPIO_BASE)
|
| 462 |
|
|
#define GPCR2_OFFS (PXA2X0_GPCR2-PXA2X0_GPIO_BASE)
|
| 463 |
|
|
#define GPDR0_OFFS (PXA2X0_GPDR0-PXA2X0_GPIO_BASE)
|
| 464 |
|
|
#define GPDR1_OFFS (PXA2X0_GPDR1-PXA2X0_GPIO_BASE)
|
| 465 |
|
|
#define GPDR2_OFFS (PXA2X0_GPDR2-PXA2X0_GPIO_BASE)
|
| 466 |
|
|
#define GAFR0_L_OFFS (PXA2X0_GAFR0_L-PXA2X0_GPIO_BASE)
|
| 467 |
|
|
#define GAFR0_U_OFFS (PXA2X0_GAFR0_U-PXA2X0_GPIO_BASE)
|
| 468 |
|
|
#define GAFR1_L_OFFS (PXA2X0_GAFR1_L-PXA2X0_GPIO_BASE)
|
| 469 |
|
|
#define GAFR1_U_OFFS (PXA2X0_GAFR1_U-PXA2X0_GPIO_BASE)
|
| 470 |
|
|
#define GAFR2_L_OFFS (PXA2X0_GAFR2_L-PXA2X0_GPIO_BASE)
|
| 471 |
|
|
#define GAFR2_U_OFFS (PXA2X0_GAFR2_U-PXA2X0_GPIO_BASE)
|
| 472 |
|
|
#define PSSR_OFFS (PXA2X0_PSSR-PXA2X0_PM_BASE)
|
| 473 |
|
|
|
| 474 |
|
|
.macro init_mpc_gpio
|
| 475 |
|
|
ldr r1, =PXA2X0_GPIO_BASE
|
| 476 |
|
|
|
| 477 |
|
|
ldr r0, =GPSR0_VAL // set GPIO outputs to default
|
| 478 |
|
|
str r0, [r1, #GPSR0_OFFS]
|
| 479 |
|
|
mvn r0, r0
|
| 480 |
|
|
str r0, [r1, #GPCR0_OFFS]
|
| 481 |
|
|
ldr r0, =GPSR1_VAL // set GPIO outputs to default
|
| 482 |
|
|
str r0, [r1, #GPSR1_OFFS]
|
| 483 |
|
|
mvn r0, r0
|
| 484 |
|
|
str r0, [r1, #GPCR1_OFFS]
|
| 485 |
|
|
ldr r0, =GPSR2_VAL // set GPIO outputs to default
|
| 486 |
|
|
str r0, [r1, #GPSR2_OFFS]
|
| 487 |
|
|
mvn r0, r0
|
| 488 |
|
|
str r0, [r1, #GPCR2_OFFS]
|
| 489 |
|
|
|
| 490 |
|
|
ldr r0, =GPDR0_VAL // GPIO direction
|
| 491 |
|
|
str r0, [r1, #GPDR0_OFFS]
|
| 492 |
|
|
ldr r0, =GPDR1_VAL // GPIO direction
|
| 493 |
|
|
str r0, [r1, #GPDR1_OFFS]
|
| 494 |
|
|
ldr r0, =GPDR2_VAL // GPIO direction
|
| 495 |
|
|
str r0, [r1, #GPDR2_OFFS]
|
| 496 |
|
|
|
| 497 |
|
|
ldr r0, =GAFR0_L_VAL // GPIO alternate function
|
| 498 |
|
|
str r0, [r1, #GAFR0_L_OFFS]
|
| 499 |
|
|
ldr r0, =GAFR0_U_VAL // GPIO alternate function
|
| 500 |
|
|
str r0, [r1, #GAFR0_U_OFFS]
|
| 501 |
|
|
ldr r0, =GAFR1_L_VAL // GPIO alternate function
|
| 502 |
|
|
str r0, [r1, #GAFR1_L_OFFS]
|
| 503 |
|
|
ldr r0, =GAFR1_U_VAL // GPIO alternate function
|
| 504 |
|
|
str r0, [r1, #GAFR1_U_OFFS]
|
| 505 |
|
|
ldr r0, =GAFR2_L_VAL // GPIO alternate function
|
| 506 |
|
|
str r0, [r1, #GAFR2_L_OFFS]
|
| 507 |
|
|
ldr r0, =GAFR2_U_VAL // GPIO alternate function
|
| 508 |
|
|
str r0, [r1, #GAFR2_U_OFFS]
|
| 509 |
|
|
|
| 510 |
|
|
ldr r1, =PXA2X0_PM_BASE
|
| 511 |
|
|
ldr r0, =0x20
|
| 512 |
|
|
str r0, [r1, #PSSR_OFFS] // enable GPIO inputs
|
| 513 |
|
|
|
| 514 |
|
|
.endm
|
| 515 |
|
|
|
| 516 |
|
|
/**********************************************************************************************************************
|
| 517 |
|
|
* LED
|
| 518 |
|
|
**********************************************************************************************************************/
|
| 519 |
|
|
// -7-
|
| 520 |
|
|
// | |
|
| 521 |
|
|
// 1 6
|
| 522 |
|
|
// | |
|
| 523 |
|
|
// -2-
|
| 524 |
|
|
// | |
|
| 525 |
|
|
// 3 5
|
| 526 |
|
|
// | |
|
| 527 |
|
|
// -4- 0
|
| 528 |
|
|
|
| 529 |
|
|
#define CYGHWR_LED_MACRO \
|
| 530 |
|
|
b 2f ;\
|
| 531 |
|
|
1: ;\
|
| 532 |
|
|
.byte 0xfb, 0x61, 0xdd, 0xf5 ;\
|
| 533 |
|
|
.byte 0x67, 0xb7, 0xbf, 0xe1 ;\
|
| 534 |
|
|
.byte 0xff, 0xf7, 0xef, 0x3f ;\
|
| 535 |
|
|
.byte 0x1d, 0x7d, 0x9f, 0x8f ;\
|
| 536 |
|
|
2: ;\
|
| 537 |
|
|
ldr r1, =PXA2X0_GPIO_BASE ;\
|
| 538 |
|
|
mov r0, #0x00ff0000 ;\
|
| 539 |
|
|
str r0, [r1, #GPSR1_OFFS] ;\
|
| 540 |
|
|
sub r0, pc, #((3f+4)-1b) ;\
|
| 541 |
|
|
3: ;\
|
| 542 |
|
|
ldrb r0, [r0, #\x] ;\
|
| 543 |
|
|
mov r0, r0, lsl #16 ;\
|
| 544 |
|
|
str r0, [r1, #GPCR1_OFFS] ;
|
| 545 |
|
|
|
| 546 |
|
|
/**********************************************************************************************************************
|
| 547 |
|
|
* initialize controller
|
| 548 |
|
|
**********************************************************************************************************************/
|
| 549 |
|
|
|
| 550 |
|
|
#if defined(CYG_HAL_STARTUP_ROM)
|
| 551 |
|
|
#define PLATFORM_SETUP1 _platform_setup1
|
| 552 |
|
|
#define CYGHWR_HAL_ARM_HAS_MMU
|
| 553 |
|
|
#else
|
| 554 |
|
|
#define PLATFORM_SETUP1
|
| 555 |
|
|
#endif
|
| 556 |
|
|
|
| 557 |
|
|
.macro _platform_setup1
|
| 558 |
|
|
.rept 0x20/4
|
| 559 |
|
|
nop
|
| 560 |
|
|
.endr
|
| 561 |
|
|
b 1f
|
| 562 |
|
|
|
| 563 |
|
|
.globl mpc50_static_info // Space for some static information
|
| 564 |
|
|
mpc50_static_info:
|
| 565 |
|
|
.byte 'M','P','C','5' // Magic
|
| 566 |
|
|
.rept 16
|
| 567 |
|
|
.long 0
|
| 568 |
|
|
.endr
|
| 569 |
|
|
1:
|
| 570 |
|
|
init_mmu_off // MMU on (and Cache)
|
| 571 |
|
|
init_mpc_gpio // GPIOs
|
| 572 |
|
|
LED(12)
|
| 573 |
|
|
init_sdram_cnt // SDRAM
|
| 574 |
|
|
LED(11)
|
| 575 |
|
|
init_intc_cnt // Interrupt Controller
|
| 576 |
|
|
LED(10)
|
| 577 |
|
|
init_clks // Clocks
|
| 578 |
|
|
LED(9)
|
| 579 |
|
|
init_mmu_cache_on // MMU and Cache
|
| 580 |
|
|
LED(8)
|
| 581 |
|
|
.endm
|
| 582 |
|
|
|
| 583 |
|
|
#endif /* CYGONCE_HAL_PLATFORM_SETUP_H */
|
| 584 |
|
|
|
