OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [rtos/] [ecos-2.0/] [packages/] [hal/] [arm/] [xscale/] [npwr/] [v2_0/] [include/] [pkgconf/] [mlt_arm_xscale_npwr_ram.h] - Blame information for rev 174

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 27 unneback
// eCos memory layout - Tue Sep 05 16:58:21 2000
2
 
3
// This is a generated file - do not edit
4
 
5
#ifndef __ASSEMBLER__
6
#include <cyg/infra/cyg_type.h>
7
#include <stddef.h>
8
 
9
#endif
10
#define CYGMEM_REGION_ram (0xA0000000)
11
#define CYGMEM_REGION_ram_SIZE (0x2000000)
12
#define CYGMEM_REGION_ram_ATTR (CYGMEM_REGION_ATTR_R | CYGMEM_REGION_ATTR_W)
13
#ifndef __ASSEMBLER__
14
extern char CYG_LABEL_NAME (__heap1) [];
15
#endif
16
#define CYGMEM_SECTION_heap1 (CYG_LABEL_NAME (__heap1))
17
#define CYGMEM_SECTION_heap1_SIZE (0xa2000000 - (size_t) CYG_LABEL_NAME (__heap1))
18
#ifndef __ASSEMBLER__
19
extern char CYG_LABEL_NAME (__pci_window) [];
20
#endif
21
//#define CYGMEM_SECTION_pci_window (CYG_LABEL_NAME (__pci_window))
22
//#define CYGMEM_SECTION_pci_window_SIZE (0x100000)

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.