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##=============================================================================
##
##      vectors.S
##
##      CalmRISC16 exception vectors
##
##=============================================================================
#####ECOSGPLCOPYRIGHTBEGIN####
## -------------------------------------------
## This file is part of eCos, the Embedded Configurable Operating System.
## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
##
## eCos is free software; you can redistribute it and/or modify it under
## the terms of the GNU General Public License as published by the Free
## Software Foundation; either version 2 or (at your option) any later version.
##
## eCos is distributed in the hope that it will be useful, but WITHOUT ANY
## WARRANTY; without even the implied warranty of MERCHANTABILITY or
## FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
## for more details.
##
## You should have received a copy of the GNU General Public License along
## with eCos; if not, write to the Free Software Foundation, Inc.,
## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
##
## As a special exception, if other files instantiate templates or use macros
## or inline functions from this file, or you compile this file and link it
## with other works to produce a work based on this file, this file does not
## by itself cause the resulting work to be covered by the GNU General Public
## License. However the source code for this file must still be made available
## in accordance with section (3) of the GNU General Public License.
##
## This exception does not invalidate any other reasons why a work based on
## this file might be covered by the GNU General Public License.
##
## Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
## at http://sources.redhat.com/ecos/ecos-license/
## -------------------------------------------
#####ECOSGPLCOPYRIGHTEND####
##=============================================================================
#######DESCRIPTIONBEGIN####
##
## Author(s):   msalter
## Contributors: msalter
## Date:        2001-02-12
## Purpose:     CalmRISC16 exception vectors
## Description: This file defines the code placed into the exception
##              vectors. It also contains the first level default VSRs
##              that save and restore state for both exceptions and
##              interrupts.
##
######DESCRIPTIONEND####
##
##=============================================================================
 
#include 
#include 
 
#ifdef CYGPKG_KERNEL
# include 
#endif
 
#include 
#include 
 
##-----------------------------------------------------------------------------
## Hardware supplied vectors
 
//==========================================================================
// Hardware exception vectors.
//   This entire section will be copied to location 0x0000 at startup time.
//
        .section ".vectors","ax"
        .global SYM_NAME(reset_vector)
SYM_NAME(reset_vector):
        .short  0x100   ; reset
        .short  0x110   ; fiq
        .short  0x120   ; irq
        .short  0x130   ; trq
        .rept 62
        brad    0f      ; swi
         nop
        .endr
 
        ;; 0x100 - reset
        ld      a8,SYM_NAME(_start)
        jmp     a8
 
        .p2align 4
        ;; 0x110 - fiq
        push    a8
        ld      a8,0
        ldw     a8,@[a8+0]
        jmp     a8
 
        .p2align 4
        ;; 0x120 - irq
        push    a8
        ld      a8,0
        ldw     a8,@[a8+4]
        jmp     a8
 
        .p2align 4
        ;; 0x130 - trq
        push    a8
        ld      a8,0
        ldw     a8,@[a8+8]
        jmp     a8
 
        .p2align 4
        ;; 0x140 - swi
  0:
        push    a8
        ld      a8,0
        ldw     a8,@[a8+12]
        jmp     a8
 
##-----------------------------------------------------------------------------
## Startup code
 
        .text
 
FUNC_START _start
        ld      r0,0
        cld     #28,r0
        cld     #29,r0
        cld     #30,r0
        cld     #31,r0
  2:
        # Initialize hardware
        hal_cpu_init
        hal_diag_init
        hal_memc_init
        hal_cache_init
        hal_timer_init
 
        # load initial stack pointer
        ld      sp,__startup_stack
 
        hal_mon_init
 
#ifdef CYG_HAL_STARTUP_ROM
        # Copy data from ROM to RAM
 
        .extern SYM_NAME(hal_copy_data)
        jsr     SYM_NAME(hal_copy_data)
#endif
        # Zero BSS
 
        .extern SYM_NAME(hal_zero_bss)
        jsr     SYM_NAME(hal_zero_bss)
 
        # Call variant and platform HAL
        # initialization routines.
 
        .extern SYM_NAME(hal_variant_init)
        jsr     SYM_NAME(hal_variant_init)
 
        .extern SYM_NAME(hal_platform_init)
        jsr     SYM_NAME(hal_platform_init)
 
        # Call constructors
        .extern SYM_NAME(cyg_hal_invoke_constructors)
        jsr     SYM_NAME(cyg_hal_invoke_constructors)
 
#if defined(CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS)
        .extern SYM_NAME(initialize_stub)
        jsr     SYM_NAME(initialize_stub)
#endif
#if defined(CYGDBG_HAL_CALM16_DEBUG_GDB_CTRLC_SUPPORT)
        .extern SYM_NAME(hal_ctrlc_isr_init)
        jsr     SYM_NAME(hal_ctrlc_isr_init)
#endif
 
        # Call cyg_start
        setsr   fe
        setsr   ie
 
        .extern SYM_NAME(cyg_start)
        ld      lr,SYM_NAME(_start)
        jmp     SYM_NAME(cyg_start)
 
FUNC_END _start
 
#if 0
FUNC_START __txchar
        ldw     r0,@[sp+2]
    99:
        cld     r6,#29
        cmp     eq,r6,#0
        brfd    99b
         nop
        cld     #30,r0
        ld      r6,1
        cld     #29,r6
        jmp     lr
FUNC_END __txchar
#endif
 
        .macro switch_stack_and_save_regs
        // a8 already pushed on the current stack
        push    r0
 
        ld      r0,e15
        and     r0,#0x3f
        cmp     ugt,r0,#%hi(__GDB_stack)
        brt     80f
        // sp <= __GDB_stack
        cmp     eq,r0,#%hi(__GDB_stack)
        brf     80f
        // %hi(sp) == %hi(__GDB_stack)
        ld      a8,#__GDB_stack
        cmp     ugt,r15,r8
        brt     80f
        // don't need switch
        pop     r0
        pop     a8
        sub     sp,#4
        push    a14
        ld      a14,sp
        add     a14,#8
        ldw     @[sp+6],a14
        bra     85f
   80:
        // switch to GDB stack
        pop     r0
        ld      a8,sp
        ld      sp,#__GDB_stack
        add     a8,#4
        push    a8
        push    a14
        sub     a8,#2
        ldw     a8,@[a8+0]
   85:
        // at this point, we're using the correct stack
        // and a15/a14 have been pushed
        push    a13,a12
        push    a11,a10
        push    a9,a8
        push    r7,r6
        push    r5,r4
        push    r3,r2
        push    r1,r0
 
        ld      r0,ssr_swi
        push    r0
        ld      r0,ssr_irq
        push    r0
        ld      r0,ssr_fiq
        push    r0
        ld      r0,spcl_irq
        push    r0
        ld      r0,spch_irq
        push    r0
        ld      r0,spcl_fiq
        push    r0
        ld      r0,spch_fiq
        push    r0
        .endm //  switch_stack_and_save_regs
 
 
        .macro restore_regs
        pop     r0
        ld      spch_fiq,r0
        pop     r0
        ld      spcl_fiq,r0
        pop     r0
        ld      spch_irq,r0
        pop     r0
        ld      spcl_irq,r0
        pop     r0
        ld      ssr_fiq,r0
        pop     r0
        ld      ssr_irq,r0
        pop     r0
        ld      ssr_swi,r0
 
        pop     r0,r1
        pop     r2,r3
        pop     r4,r5
        pop     r6,r7
        pop     a8,a9
        pop     a10,a11
        pop     a12,a13
        pop     a14
        ldw     sp,@[sp+2]
        .endm
 
##------------------------------------------------------------------------------
## Default interrupt VSR.
## Saves machine state and calls appropriate ISR.
 
FUNC_START __default_irq_vsr
 
        // IRQ is overloaded for use by the break insn.
        // For RedBoot (or any stub) on the core eval boards, we treat
        // IRQ as an exception.
 
        switch_stack_and_save_regs
        ld      r0,2
        push    r0
 
#if 0
        // push interrupt_data arg
 
        ld      a8,#SYM_NAME(hal_interrupt_data)
        ldw     a8,@[a8 + 4]
        push    a8
 
        // push vector arg
        push    r0
        ld      r0,0
        push    r0
 
        // call handler
        ld      a8,#SYM_NAME(hal_interrupt_handlers)
        ldw     a8,@[a8 + 4]
        jsr     a8
        add     sp,#10
#else
        // call exception handler
        ld      a8,sp
        add     a8,#2
        push    a8
        jsr     SYM_NAME(cyg_hal_exception_handler)
        add     sp,#6
#endif
 
        restore_regs
        ret_irq
FUNC_END   __default_irq_vsr
 
##------------------------------------------------------------------------------
## Default fast interrupt VSR.
## Saves machine state and calls appropriate ISR.
 
FUNC_START __default_fiq_vsr
 
        switch_stack_and_save_regs
        ld      r0,1
        push    r0
 
        // push interrupt_data arg
        ld      a8,#SYM_NAME(hal_interrupt_data)
        ldw     a8,@[a8 + 0]
        push    a8
 
        // push vector arg
        push    r0
        ld      r0,0
        push    r0
 
        // call handler
        ld      a8,#SYM_NAME(hal_interrupt_handlers)
        ldw     a8,@[a8 + 0]
        jsr     a8
        add     sp,#10
 
        restore_regs
        ret_fiq
FUNC_END   __default_fiq_vsr
 
##------------------------------------------------------------------------------
## Default trace VSR.
## Saves machine state and calls appropriate handler.
 
FUNC_START __default_trq_vsr
        switch_stack_and_save_regs
        ld      r0,3
        push    r0
 
        // call exception handler
        ld      a8,sp
        add     a8,#2
        push    a8
        jsr     SYM_NAME(cyg_hal_exception_handler)
        add     sp,#6
 
        restore_regs
        ret_irq
FUNC_END   __default_trq_vsr
 
##------------------------------------------------------------------------------
## Default swi VSR.
## Saves machine state and calls appropriate handler.
 
FUNC_START __default_swi_vsr
        switch_stack_and_save_regs
        ld      r0,4
        push    r0
 
        // call exception handler
        ld      a8,sp
        add     a8,#2
        push    a8
        jsr     SYM_NAME(cyg_hal_exception_handler)
        add     sp,#6
 
        restore_regs
        ret_swi
FUNC_END   __default_swi_vsr
 
##-----------------------------------------------------------------------------
## Short circuit in case any code tries to use "__gccmain()"
 
FUNC_START __gccmain
        jmp     lr
FUNC_END __gccmain
 
##-----------------------------------------------------------------------------
## Stacks.
## Used during intialization and for executing ISRs.
 
        .section ".bss"
 
#ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
        .p2align 2
__GDB_stack_base:
        .rept 0x1000
        .byte 0
        .endr
__GDB_stack:
        .long   0
#endif
        .p2align 2
__startup_stack_base:
        .rept 0x1000
        .byte 0
        .endr
        .p2align 2
__startup_stack:
        .long   0
 
##-----------------------------------------------------------------------------
## VSR table.
## The main interrupt code indirects through here to find the VSR
## to execute for each architecture defined interrupt.
## This is only used for simulated targets, on real targets a fixed location VSR
## table is now allocated at 0x000000.
 
#ifndef CYG_HAL_CALM16_VSR_TABLE_DEFINED
 
##      .section ".vsr_table","a"
 
        .data
 
        .globl  SYM_NAME(hal_vsr_table)
 
SYM_NAME(hal_vsr_table):
        .long   SYM_NAME(__default_fiq_vsr)     // FIQ
        .long   SYM_NAME(__default_irq_vsr)     // IRQ
        .long   SYM_NAME(__default_trq_vsr)     // TRQ
        .long   SYM_NAME(__default_swi_vsr)     // SWI
#endif
 
        .data
        .balign 16
#ifdef CYGSEM_HAL_VIRTUAL_VECTOR_SUPPORT
        // Vectors used to communicate between eCos and ROM environments
        .globl  SYM_NAME(hal_virtual_vector_table)
SYM_NAME(hal_virtual_vector_table):
        .rept   64
        .long   0
        .endr
#endif
 
#------------------------------------------------------------------------------
# Interrupt vector tables.
# These tables contain the isr, data and object pointers used to deliver
# interrupts to user code.
# hal_interrupt_level contains the interrupt level set by
# HAL_INTERRUPT_CONFIGURE().
# This is a default set that provide support only for the single external
# interrupt. Platforms or boards are expected to define their own versions
# of these if they have their own interrupt mappings.
 
#ifndef CYG_HAL_CALM16_ISR_TABLES_DEFINED
 
        .extern SYM_NAME(hal_default_isr)
 
        .data
 
        .globl  SYM_NAME(hal_interrupt_handlers)
SYM_NAME(hal_interrupt_handlers):
        .long   SYM_NAME(hal_default_isr)
        .long   SYM_NAME(hal_default_isr)
 
 
        .globl  SYM_NAME(hal_interrupt_data)
SYM_NAME(hal_interrupt_data):
        .long   0
        .long   0
 
        .globl  SYM_NAME(hal_interrupt_objects)
SYM_NAME(hal_interrupt_objects):
        .long   0
        .long   0
 
#endif
 
##-----------------------------------------------------------------------------
## end of vectors.S
 
 

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[/] [openrisc/] [trunk/] [rtos/] [ecos-2.0/] [packages/] [hal/] [calmrisc16/] [arch/] [v2_0/] [src/] [vectors.S] - Blame information for rev 773

Line No.	Rev	Author	Line
1	27	unneback	`##=============================================================================`
2			`##`
3			`## vectors.S`
4			`##`
5			`## CalmRISC16 exception vectors`
6			`##`
7			`##=============================================================================`
8			`#####ECOSGPLCOPYRIGHTBEGIN####`
9			`## -------------------------------------------`
10			`## This file is part of eCos, the Embedded Configurable Operating System.`
11			`## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.`
12			`##`
13			`## eCos is free software; you can redistribute it and/or modify it under`
14			`## the terms of the GNU General Public License as published by the Free`
15			`## Software Foundation; either version 2 or (at your option) any later version.`
16			`##`
17			`## eCos is distributed in the hope that it will be useful, but WITHOUT ANY`
18			`## WARRANTY; without even the implied warranty of MERCHANTABILITY or`
19			`## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License`
20			`## for more details.`
21			`##`
22			`## You should have received a copy of the GNU General Public License along`
23			`## with eCos; if not, write to the Free Software Foundation, Inc.,`
24			`## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.`
25			`##`
26			`## As a special exception, if other files instantiate templates or use macros`
27			`## or inline functions from this file, or you compile this file and link it`
28			`## with other works to produce a work based on this file, this file does not`
29			`## by itself cause the resulting work to be covered by the GNU General Public`
30			`## License. However the source code for this file must still be made available`
31			`## in accordance with section (3) of the GNU General Public License.`
32			`##`
33			`## This exception does not invalidate any other reasons why a work based on`
34			`## this file might be covered by the GNU General Public License.`
35			`##`
36			`## Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.`
37			`## at http://sources.redhat.com/ecos/ecos-license/`
38			`## -------------------------------------------`
39			`#####ECOSGPLCOPYRIGHTEND####`
40			`##=============================================================================`
41			`#######DESCRIPTIONBEGIN####`
42			`##`
43			`## Author(s): msalter`
44			`## Contributors: msalter`
45			`## Date: 2001-02-12`
46			`## Purpose: CalmRISC16 exception vectors`
47			`## Description: This file defines the code placed into the exception`
48			`## vectors. It also contains the first level default VSRs`
49			`## that save and restore state for both exceptions and`
50			`## interrupts.`
51			`##`
52			`######DESCRIPTIONEND####`
53			`##`
54			`##=============================================================================`
55
56			`#include`
57			`#include`
58
59			`#ifdef CYGPKG_KERNEL`
60			`# include`
61			`#endif`
62
63			`#include`
64			`#include`
65
66			`##-----------------------------------------------------------------------------`
67			`## Hardware supplied vectors`
68
69			`//==========================================================================`
70			`// Hardware exception vectors.`
71			`// This entire section will be copied to location 0x0000 at startup time.`
72			`//`
73			`.section ".vectors","ax"`
74			`.global SYM_NAME(reset_vector)`
75			`SYM_NAME(reset_vector):`
76			`.short 0x100 ; reset`
77			`.short 0x110 ; fiq`
78			`.short 0x120 ; irq`
79			`.short 0x130 ; trq`
80			`.rept 62`
81			`brad 0f ; swi`
82			`nop`
83			`.endr`
84
85			`;; 0x100 - reset`
86			`ld a8,SYM_NAME(_start)`
87			`jmp a8`
88
89			`.p2align 4`
90			`;; 0x110 - fiq`
91			`push a8`
92			`ld a8,0`
93			`ldw a8,@[a8+0]`
94			`jmp a8`
95
96			`.p2align 4`
97			`;; 0x120 - irq`
98			`push a8`
99			`ld a8,0`
100			`ldw a8,@[a8+4]`
101			`jmp a8`
102
103			`.p2align 4`
104			`;; 0x130 - trq`
105			`push a8`
106			`ld a8,0`
107			`ldw a8,@[a8+8]`
108			`jmp a8`
109
110			`.p2align 4`
111			`;; 0x140 - swi`
112			`0:`
113			`push a8`
114			`ld a8,0`
115			`ldw a8,@[a8+12]`
116			`jmp a8`
117
118			`##-----------------------------------------------------------------------------`
119			`## Startup code`
120
121			`.text`
122
123			`FUNC_START _start`
124			`ld r0,0`
125			`cld #28,r0`
126			`cld #29,r0`
127			`cld #30,r0`
128			`cld #31,r0`
129			`2:`
130			`# Initialize hardware`
131			`hal_cpu_init`
132			`hal_diag_init`
133			`hal_memc_init`
134			`hal_cache_init`
135			`hal_timer_init`
136
137			`# load initial stack pointer`
138			`ld sp,__startup_stack`
139
140			`hal_mon_init`
141
142			`#ifdef CYG_HAL_STARTUP_ROM`
143			`# Copy data from ROM to RAM`
144
145			`.extern SYM_NAME(hal_copy_data)`
146			`jsr SYM_NAME(hal_copy_data)`
147			`#endif`
148			`# Zero BSS`
149
150			`.extern SYM_NAME(hal_zero_bss)`
151			`jsr SYM_NAME(hal_zero_bss)`
152
153			`# Call variant and platform HAL`
154			`# initialization routines.`
155
156			`.extern SYM_NAME(hal_variant_init)`
157			`jsr SYM_NAME(hal_variant_init)`
158
159			`.extern SYM_NAME(hal_platform_init)`
160			`jsr SYM_NAME(hal_platform_init)`
161
162			`# Call constructors`
163			`.extern SYM_NAME(cyg_hal_invoke_constructors)`
164			`jsr SYM_NAME(cyg_hal_invoke_constructors)`
165
166			`#if defined(CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS)`
167			`.extern SYM_NAME(initialize_stub)`
168			`jsr SYM_NAME(initialize_stub)`
169			`#endif`
170			`#if defined(CYGDBG_HAL_CALM16_DEBUG_GDB_CTRLC_SUPPORT)`
171			`.extern SYM_NAME(hal_ctrlc_isr_init)`
172			`jsr SYM_NAME(hal_ctrlc_isr_init)`
173			`#endif`
174
175			`# Call cyg_start`
176			`setsr fe`
177			`setsr ie`
178
179			`.extern SYM_NAME(cyg_start)`
180			`ld lr,SYM_NAME(_start)`
181			`jmp SYM_NAME(cyg_start)`
182
183			`FUNC_END _start`
184
185			`#if 0`
186			`FUNC_START __txchar`
187			`ldw r0,@[sp+2]`
188			`99:`
189			`cld r6,#29`
190			`cmp eq,r6,#0`
191			`brfd 99b`
192			`nop`
193			`cld #30,r0`
194			`ld r6,1`
195			`cld #29,r6`
196			`jmp lr`
197			`FUNC_END __txchar`
198			`#endif`
199
200			`.macro switch_stack_and_save_regs`
201			`// a8 already pushed on the current stack`
202			`push r0`
203
204			`ld r0,e15`
205			`and r0,#0x3f`
206			`cmp ugt,r0,#%hi(__GDB_stack)`
207			`brt 80f`
208			`// sp <= __GDB_stack`
209			`cmp eq,r0,#%hi(__GDB_stack)`
210			`brf 80f`
211			`// %hi(sp) == %hi(__GDB_stack)`
212			`ld a8,#__GDB_stack`
213			`cmp ugt,r15,r8`
214			`brt 80f`
215			`// don't need switch`
216			`pop r0`
217			`pop a8`
218			`sub sp,#4`
219			`push a14`
220			`ld a14,sp`
221			`add a14,#8`
222			`ldw @[sp+6],a14`
223			`bra 85f`
224			`80:`
225			`// switch to GDB stack`
226			`pop r0`
227			`ld a8,sp`
228			`ld sp,#__GDB_stack`
229			`add a8,#4`
230			`push a8`
231			`push a14`
232			`sub a8,#2`
233			`ldw a8,@[a8+0]`
234			`85:`
235			`// at this point, we're using the correct stack`
236			`// and a15/a14 have been pushed`
237			`push a13,a12`
238			`push a11,a10`
239			`push a9,a8`
240			`push r7,r6`
241			`push r5,r4`
242			`push r3,r2`
243			`push r1,r0`
244
245			`ld r0,ssr_swi`
246			`push r0`
247			`ld r0,ssr_irq`
248			`push r0`
249			`ld r0,ssr_fiq`
250			`push r0`
251			`ld r0,spcl_irq`
252			`push r0`
253			`ld r0,spch_irq`
254			`push r0`
255			`ld r0,spcl_fiq`
256			`push r0`
257			`ld r0,spch_fiq`
258			`push r0`
259			`.endm // switch_stack_and_save_regs`
260
261
262			`.macro restore_regs`
263			`pop r0`
264			`ld spch_fiq,r0`
265			`pop r0`
266			`ld spcl_fiq,r0`
267			`pop r0`
268			`ld spch_irq,r0`
269			`pop r0`
270			`ld spcl_irq,r0`
271			`pop r0`
272			`ld ssr_fiq,r0`
273			`pop r0`
274			`ld ssr_irq,r0`
275			`pop r0`
276			`ld ssr_swi,r0`
277
278			`pop r0,r1`
279			`pop r2,r3`
280			`pop r4,r5`
281			`pop r6,r7`
282			`pop a8,a9`
283			`pop a10,a11`
284			`pop a12,a13`
285			`pop a14`
286			`ldw sp,@[sp+2]`
287			`.endm`
288
289			`##------------------------------------------------------------------------------`
290			`## Default interrupt VSR.`
291			`## Saves machine state and calls appropriate ISR.`
292
293			`FUNC_START __default_irq_vsr`
294
295			`// IRQ is overloaded for use by the break insn.`
296			`// For RedBoot (or any stub) on the core eval boards, we treat`
297			`// IRQ as an exception.`
298
299			`switch_stack_and_save_regs`
300			`ld r0,2`
301			`push r0`
302
303			`#if 0`
304			`// push interrupt_data arg`
305
306			`ld a8,#SYM_NAME(hal_interrupt_data)`
307			`ldw a8,@[a8 + 4]`
308			`push a8`
309
310			`// push vector arg`
311			`push r0`
312			`ld r0,0`
313			`push r0`
314
315			`// call handler`
316			`ld a8,#SYM_NAME(hal_interrupt_handlers)`
317			`ldw a8,@[a8 + 4]`
318			`jsr a8`
319			`add sp,#10`
320			`#else`
321			`// call exception handler`
322			`ld a8,sp`
323			`add a8,#2`
324			`push a8`
325			`jsr SYM_NAME(cyg_hal_exception_handler)`
326			`add sp,#6`
327			`#endif`
328
329			`restore_regs`
330			`ret_irq`
331			`FUNC_END __default_irq_vsr`
332
333			`##------------------------------------------------------------------------------`
334			`## Default fast interrupt VSR.`
335			`## Saves machine state and calls appropriate ISR.`
336
337			`FUNC_START __default_fiq_vsr`
338
339			`switch_stack_and_save_regs`
340			`ld r0,1`
341			`push r0`
342
343			`// push interrupt_data arg`
344			`ld a8,#SYM_NAME(hal_interrupt_data)`
345			`ldw a8,@[a8 + 0]`
346			`push a8`
347
348			`// push vector arg`
349			`push r0`
350			`ld r0,0`
351			`push r0`
352
353			`// call handler`
354			`ld a8,#SYM_NAME(hal_interrupt_handlers)`
355			`ldw a8,@[a8 + 0]`
356			`jsr a8`
357			`add sp,#10`
358
359			`restore_regs`
360			`ret_fiq`
361			`FUNC_END __default_fiq_vsr`
362
363			`##------------------------------------------------------------------------------`
364			`## Default trace VSR.`
365			`## Saves machine state and calls appropriate handler.`
366
367			`FUNC_START __default_trq_vsr`
368			`switch_stack_and_save_regs`
369			`ld r0,3`
370			`push r0`
371
372			`// call exception handler`
373			`ld a8,sp`
374			`add a8,#2`
375			`push a8`
376			`jsr SYM_NAME(cyg_hal_exception_handler)`
377			`add sp,#6`
378
379			`restore_regs`
380			`ret_irq`
381			`FUNC_END __default_trq_vsr`
382
383			`##------------------------------------------------------------------------------`
384			`## Default swi VSR.`
385			`## Saves machine state and calls appropriate handler.`
386
387			`FUNC_START __default_swi_vsr`
388			`switch_stack_and_save_regs`
389			`ld r0,4`
390			`push r0`
391
392			`// call exception handler`
393			`ld a8,sp`
394			`add a8,#2`
395			`push a8`
396			`jsr SYM_NAME(cyg_hal_exception_handler)`
397			`add sp,#6`
398
399			`restore_regs`
400			`ret_swi`
401			`FUNC_END __default_swi_vsr`
402
403			`##-----------------------------------------------------------------------------`
404			`## Short circuit in case any code tries to use "__gccmain()"`
405
406			`FUNC_START __gccmain`
407			`jmp lr`
408			`FUNC_END __gccmain`
409
410			`##-----------------------------------------------------------------------------`
411			`## Stacks.`
412			`## Used during intialization and for executing ISRs.`
413
414			`.section ".bss"`
415
416			`#ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS`
417			`.p2align 2`
418			`__GDB_stack_base:`
419			`.rept 0x1000`
420			`.byte 0`
421			`.endr`
422			`__GDB_stack:`
423			`.long 0`
424			`#endif`
425			`.p2align 2`
426			`__startup_stack_base:`
427			`.rept 0x1000`
428			`.byte 0`
429			`.endr`
430			`.p2align 2`
431			`__startup_stack:`
432			`.long 0`
433
434			`##-----------------------------------------------------------------------------`
435			`## VSR table.`
436			`## The main interrupt code indirects through here to find the VSR`
437			`## to execute for each architecture defined interrupt.`
438			`## This is only used for simulated targets, on real targets a fixed location VSR`
439			`## table is now allocated at 0x000000.`
440
441			`#ifndef CYG_HAL_CALM16_VSR_TABLE_DEFINED`
442
443			`## .section ".vsr_table","a"`
444
445			`.data`
446
447			`.globl SYM_NAME(hal_vsr_table)`
448
449			`SYM_NAME(hal_vsr_table):`
450			`.long SYM_NAME(__default_fiq_vsr) // FIQ`
451			`.long SYM_NAME(__default_irq_vsr) // IRQ`
452			`.long SYM_NAME(__default_trq_vsr) // TRQ`
453			`.long SYM_NAME(__default_swi_vsr) // SWI`
454			`#endif`
455
456			`.data`
457			`.balign 16`
458			`#ifdef CYGSEM_HAL_VIRTUAL_VECTOR_SUPPORT`
459			`// Vectors used to communicate between eCos and ROM environments`
460			`.globl SYM_NAME(hal_virtual_vector_table)`
461			`SYM_NAME(hal_virtual_vector_table):`
462			`.rept 64`
463			`.long 0`
464			`.endr`
465			`#endif`
466
467			`#------------------------------------------------------------------------------`
468			`# Interrupt vector tables.`
469			`# These tables contain the isr, data and object pointers used to deliver`
470			`# interrupts to user code.`
471			`# hal_interrupt_level contains the interrupt level set by`
472			`# HAL_INTERRUPT_CONFIGURE().`
473			`# This is a default set that provide support only for the single external`
474			`# interrupt. Platforms or boards are expected to define their own versions`
475			`# of these if they have their own interrupt mappings.`
476
477			`#ifndef CYG_HAL_CALM16_ISR_TABLES_DEFINED`
478
479			`.extern SYM_NAME(hal_default_isr)`
480
481			`.data`
482
483			`.globl SYM_NAME(hal_interrupt_handlers)`
484			`SYM_NAME(hal_interrupt_handlers):`
485			`.long SYM_NAME(hal_default_isr)`
486			`.long SYM_NAME(hal_default_isr)`
487
488
489			`.globl SYM_NAME(hal_interrupt_data)`
490			`SYM_NAME(hal_interrupt_data):`
491			`.long 0`
492			`.long 0`
493
494			`.globl SYM_NAME(hal_interrupt_objects)`
495			`SYM_NAME(hal_interrupt_objects):`
496			`.long 0`
497			`.long 0`
498
499			`#endif`
500
501			`##-----------------------------------------------------------------------------`
502			`## end of vectors.S`
503
504