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#ifndef CYGONCE_HAL_CALM32_REGS_H

#define CYGONCE_HAL_CALM32_REGS_H

//========================================================================

//

//      calm32-regs.h

//

//      Register defines for CalmRISC 16 processors

//

//========================================================================

//####ECOSGPLCOPYRIGHTBEGIN####

// -------------------------------------------

// This file is part of eCos, the Embedded Configurable Operating System.

// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.

//

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// You should have received a copy of the GNU General Public License along

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//

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// or inline functions from this file, or you compile this file and link it

// with other works to produce a work based on this file, this file does not

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// -------------------------------------------

//####ECOSGPLCOPYRIGHTEND####

//========================================================================

//#####DESCRIPTIONBEGIN####

//

// Author(s):     Red Hat, msalter

// Contributors:  Red Hat, msalter

// Date:          2001-02-12

// Purpose:       

// Description:   Register defines for CalmRISC 16 processors

// Usage:         

//

//####DESCRIPTIONEND####

//

//========================================================================

#include <pkgconf/hal.h>

#ifdef CYGARC_HAL_COMMON_EXPORT_CPU_MACROS

// This value must agree with NUMREGS in calm32-stub.h.

#define NUM_REGS 23

#define REG_SIZE 4

// Status register fields

#define SR_T            0x00000001      // TRUE flag

#define SR_V            0x00000008      // Overflow flag

#define SR_Z0           0x00000010      // R6 Zero flag

#define SR_Z1           0x00000020      // R7 Zero flag.

#define SR_DS           0x00000040      // Divisor sign

#define SR_QT           0x00000080      // Quotient

#define SR_BX           0x00001000      // Byte sign extension

#define SR_HX           0x00002000      // Halfword sign extension

#define SR_SYSX_MASK    0x000f0000      // system extension

#define SR_SYSX_SHIFT   16

#define SR_IE           0x01000000      // IRQ enable

#define SR_FE           0x02000000      // FIQ enable

#define SR_TE           0x04000000      // Trace enable

#define SR_BS           0x10000000      // FIQ enable

#define SR_RS0          0x20000000      // Register bank select

#define SR_RS1          0x40000000      // Register bank select

#define SR_PM           0x80000000      // Privilege mode

#endif // ifdef CYGARC_HAL_COMMON_EXPORT_CPU_MACROS

#endif // ifndef CYGONCE_HAL_CALM32_REGS_H