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##=============================================================================
##
##      vectors.S
##
##      CalmRISC32 exception vectors
##
##=============================================================================
#####ECOSGPLCOPYRIGHTBEGIN####
## -------------------------------------------
## This file is part of eCos, the Embedded Configurable Operating System.
## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
##
## eCos is free software; you can redistribute it and/or modify it under
## the terms of the GNU General Public License as published by the Free
## Software Foundation; either version 2 or (at your option) any later version.
##
## eCos is distributed in the hope that it will be useful, but WITHOUT ANY
## WARRANTY; without even the implied warranty of MERCHANTABILITY or
## FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
## for more details.
##
## You should have received a copy of the GNU General Public License along
## with eCos; if not, write to the Free Software Foundation, Inc.,
## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
##
## As a special exception, if other files instantiate templates or use macros
## or inline functions from this file, or you compile this file and link it
## with other works to produce a work based on this file, this file does not
## by itself cause the resulting work to be covered by the GNU General Public
## License. However the source code for this file must still be made available
## in accordance with section (3) of the GNU General Public License.
##
## This exception does not invalidate any other reasons why a work based on
## this file might be covered by the GNU General Public License.
##
## Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
## at http://sources.redhat.com/ecos/ecos-license/
## -------------------------------------------
#####ECOSGPLCOPYRIGHTEND####
##=============================================================================
#######DESCRIPTIONBEGIN####
##
## Author(s):   msalter
## Contributors: msalter
## Date:        2001-02-12
## Purpose:     CalmRISC32 exception vectors
## Description: This file defines the code placed into the exception
##              vectors. It also contains the first level default VSRs
##              that save and restore state for both exceptions and
##              interrupts.
##
######DESCRIPTIONEND####
##
##=============================================================================
 
#include 
#include 
#include 
 
#ifdef CYGPKG_KERNEL
# include 
#else
# undef CYGFUN_HAL_COMMON_KERNEL_SUPPORT
# undef CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK
#endif
 
#include 
#include 
 
        .macro  txreg reg
    99:
        cld     r0,fr29
        cmp     eq r0,#0
        brfd    99b
         nop
        cld     fr30,\reg
        ld      r0,#1
        cld     fr29,r0
        .endm
 
        .extern cyg_instrument
 
##-----------------------------------------------------------------------------
## Hardware supplied vectors
 
        .macro  cpu_vector  vsr_nr
        setsr   bs
        clrsr   rs0
        clrsr   rs1
        nop
        push    r8
        brad    __exc_trampoline
         ld     r8,#\vsr_nr
        .endm
 
##==========================================================================
## Hardware exception vectors.
##
        .section ".vectors","ax"
        .global reset_vector
reset_vector:
        ldw     r0,#_start
        jmpd    r0
         nop
 
        # 0x20 - FIQ
        .p2align 5
        cpu_vector 0
 
        # 0x40 - IRQ
        .p2align 5
        cpu_vector 1
 
        # 0x50 - COP
        .p2align 4
        cpu_vector 2
 
        # 0x60 - DABRT
        .p2align 4
        cpu_vector 3
 
        # 0x70 - IABRT
        .p2align 4
        cpu_vector 4
 
        # 0x80 - PRIV
        .p2align 4
        cpu_vector 5
 
        # 0xA0 - UNIMPL
        .p2align 5
        cpu_vector 6
 
        # 0xC0 - TRACE
        .p2align 5
        cpu_vector 7
 
        # 0x100 - SWI 0
        .p2align 6
        cpu_vector 8
 
        # SWI 1
        .p2align 4
        cpu_vector 8
 
        # SWI 2
        .p2align 4
        cpu_vector 8
 
        # SWI 3
        .p2align 4
        cpu_vector 8
 
        # SWI 4
        .p2align 4
        cpu_vector 8
 
        # SWI 5
        .p2align 4
        cpu_vector 8
 
        # SWI 6
        .p2align 4
        cpu_vector 8
 
        # SWI 7
        .p2align 4
        cpu_vector 8
 
        # SWI 8
        .p2align 4
        cpu_vector 8
 
        # SWI 9
        .p2align 4
        cpu_vector 8
 
        # SWI 10
        .p2align 4
        cpu_vector 8
 
        # SWI 11
        .p2align 4
        cpu_vector 8
 
        # SWI 12
        .p2align 4
        cpu_vector 8
 
        # SWI 13
        .p2align 4
        cpu_vector 8
 
        # SWI 14
        .p2align 4
        cpu_vector 8
 
        # SWI 15
        .p2align 4
        cpu_vector 8
 
__exc_trampoline:
        push    r8      // vsr number
        sl2     r8      // offset into vsr table
        ldw     r8,@[r8 + 0]
        jmpd    r8
         pop    r8
 
##-----------------------------------------------------------------------------
## Startup code
 
        .text
 
FUNC_START _start
        # default vector table
        ld      r0,#0
        ld      vbr,r0
 
        # ensure privileged mode with all bank1 register view
        setsr   pm
        setsr   bs
        clrsr   rs0
        clrsr   rs1
 
        # Initialize hardware
        hal_cpu_init
        hal_diag_init
        hal_memc_init
        hal_cache_init
        hal_timer_init
 
        # load initial stack pointer
        ldw     sp,#__startup_stack
 
        clrsr   bs
        nop
        ldw     sp,#__user_stack
        setsr   bs
        nop
 
        hal_mon_init
 
#ifdef CYG_HAL_STARTUP_ROM
        # Copy data from ROM to RAM
 
        .extern hal_copy_data
        ldw     r0,#hal_copy_data
        jsrd    r0
         nop
#endif
 
        # Zero BSS
 
        .extern hal_zero_bss
        ldw     r0,#hal_zero_bss
        jsrd    r0
         nop
 
        # Call variant and platform HAL
        # initialization routines.
 
        .extern hal_variant_init
        ldw     r0,#hal_variant_init
        jsrd    r0
         nop
 
        .extern hal_platform_init
        ldw     r0,#hal_platform_init
        jsrd    r0
         nop
 
        # Call constructors
        .extern cyg_hal_invoke_constructors
        ldw     r0,#cyg_hal_invoke_constructors
        jsrd     r0
         nop
 
#if defined(CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS)
        .extern initialize_stub
        ldw     r0,#initialize_stub
        jsrd     r0
         nop
#endif
 
#if defined(CYGDBG_HAL_CALM32_DEBUG_GDB_CTRLC_SUPPORT)
        .extern hal_ctrlc_isr_init
        ldw     r0,#hal_ctrlc_isr_init
        jsrd     r0
         nop
#endif
 
        # Call cyg_start
 
        .extern cyg_start
#if 0
        clrsr   pm
        nop
        clrsr   bs
        nop
#endif
        ld      fp,sp
 
        ldw     lr,#_start
        ldw     r0,#cyg_start
        jmpd    r0
         nop
FUNC_END _start
 
 
        .macro switch_stack_and_save_regs tmpvar
        // save vector number temporarily
        push    r9
        ldw     r9,#\tmpvar
        ldw     @[r9 + 0],r8
        pop     r9
 
        // Make sure we use the gdb stack
        ldw     r8,#__GDB_stack
        cmpu    gt sp,r8
        brtd    0f
         nop
        ldw     r8,#__GDB_stack_base
        cmpu    gt sp,r8
        brtd    1f
         nop
    0:
        // need to switch stack
        ld      r8,sp
        add     r8,#4
        ldw     sp,#__GDB_stack
        push    r8
        push    r14
        push    r13
        push    r12
        sub     r8,#4
        brad    2f
         ldw    r8,@[r8+0]
    1:
        // already using gdb stack
        pop     r8
        // save bank 1 regs
        push    q3
    2:
        // save rest of bank1 regs
        push    q2
        push    q1
        push    q0
 
        // save bank 0 regs
        setsr   rs1
        nop
        push    q1
        push    q0
        clrsr   rs1
        setsr   rs0
        nop
        push    q1
        push    q0
        clrsr   rs0
        nop
        // save special regs
        ld      r0,ssr_expt
        push    r0
        ld      r0,ssr_swi
        push    r0
        ld      r0,ssr_fiq
        push    r0
        ld      r0,ssr_irq
        push    r0
        ld      r0,spc_expt
        push    r0
        ld      r0,spc_swi
        push    r0
        ld      r0,spc_fiq
        push    r0
        ld      r0,spc_irq
        push    r0
        ld      r0,vbr
        push    r0
 
        ldw     r8,#\tmpvar
        ldw     r8,@[r8+0]
        push    r8
        .endm
 
        .macro restore_regs
        // discard vector
        pop     r0
        // restore special regs
        pop     r0
        ld      vbr,r0
        pop     r0
        ld      spc_irq,r0
        pop     r0
        ld      spc_fiq,r0
        pop     r0
        ld      spc_swi,r0
        pop     r0
        ld      spc_expt,r0
        pop     r0
        ld      ssr_irq,r0
        pop     r0
        ld      ssr_fiq,r0
        pop     r0
        ld      ssr_swi,r0
        pop     r0
        ld      ssr_expt,r0
        // restore bank 0 regs
        setsr   rs1
        nop
        pop     q0
        pop     q1
        clrsr   rs1
        setsr   rs0
        nop
        pop     q0
        pop     q1
        clrsr   rs0
        nop
        // restore bank 1 regs
        pop     q0
        pop     q1
        pop     q2
        pop     q3
        .endm
 
 
##-----------------------------------------------------------------------------
## Default exception VSR.
## Saves machine state and calls external handling code.
## On entry, the original R8 has been pushed on the stack and R8 now
## contains the vector number.
 
FUNC_START __default_exception_vsr
 
        switch_stack_and_save_regs __expt_temp
 
        // call exception handler
        ldw     r8,#cyg_hal_exception_handler
        jsrd    r8
         ld     r0,sp
 
        restore_regs
 
        ret_expt
         nop
 
FUNC_END   __default_exception_vsr
 
##-----------------------------------------------------------------------------
## Default swi VSR.
## Saves machine state and calls external handling code.
## On entry, the original R8 has been pushed on the stack and R8 now
## contains the vector number.
 
FUNC_START __default_swi_vsr
 
        switch_stack_and_save_regs __swi_temp
 
        // call exception handler
        ldw     r8,#cyg_hal_exception_handler
        jsrd    r8
         ld     r0,sp
 
        restore_regs
 
        ret_swi
         nop
 
FUNC_END  __default_swi_vsr
 
##------------------------------------------------------------------------------
## Default interrupt VSR.
## Saves machine state and calls appropriate ISR. When done, calls
## interrupt_end() to finish up and possibly reschedule.
 
FUNC_START __default_fiq_vsr
        switch_stack_and_save_regs __fiq_temp
 
        ldw     r8,#hal_interrupt_data
        ldw     r1,@[r8 + 0]
        ldw     r8,#hal_interrupt_handlers
        ldw     r8,@[r8 + 0]
 
        // call fiq handler
        jsrd    r8
         ld     r0,#0
 
        restore_regs
 
        ret_fiq
         nop
FUNC_END   __default_fiq_vsr
 
FUNC_START __default_irq_vsr
        switch_stack_and_save_regs __irq_temp
 
        ldw     r8,#hal_interrupt_data
        ldw     r1,@[r8 + 4]
        ldw     r8,#hal_interrupt_handlers
        ldw     r8,@[r8 + 4]
 
        // call fiq handler
        jsrd    r8
         ld     r0,#1
 
        restore_regs
 
        ret_irq
         nop
FUNC_END   __default_irq_vsr
 
##-----------------------------------------------------------------------------
## Execute pending DSRs on the interrupt stack with interrupts enabled.
## Note: this can only be called from code running on a thread stack
 
#ifdef CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK
        .extern cyg_interrupt_call_pending_DSRs
 
FUNC_START hal_interrupt_stack_call_pending_DSRs
FUNC_END hal_interrupt_stack_call_pending_DSRs
#endif
 
##-----------------------------------------------------------------------------
## Short circuit in case any code tries to use "__gccmain()"
 
FUNC_START __gccmain
        jmpd    lr
         nop
FUNC_END __gccmain
 
##-----------------------------------------------------------------------------
## Interrupt Stack.
## Used during intialization and for executing ISRs.
 
        .section ".bss"
 
        .balign 16
        .global cyg_interrupt_stack_base
cyg_interrupt_stack_base:
__interrupt_stack_base:
        .rept CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE
        .byte 0
        .endr
        .balign 16
        .global cyg_interrupt_stack
cyg_interrupt_stack:
__interrupt_stack:
 
        .long   0
 
#ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
        .balign 16
__GDB_stack_base:
        .rept 0x400
        .byte 0
        .endr
__GDB_stack:
        .long   0
#endif
        .balign 16
__startup_stack_base:
#ifdef CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK
        .rept 512
#else
        .rept CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE
#endif
        .byte 0
        .endr
        .balign 16
__startup_stack:
        .long   0
 
        .balign 16
__user_stack_base:
#ifdef CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK
        .rept 512
#else
        .rept CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE
#endif
        .byte 0
        .endr
        .balign 16
__user_stack:
        .long   0
 
__expt_temp:
        .long   0
__swi_temp:
        .long   0
__irq_temp:
        .long   0
__fiq_temp:
        .long   0
 
 
##-----------------------------------------------------------------------------
## VSR table.
## The main interrupt code indirects through here to find the VSR
## to execute for each architecture defined interrupt.
## This is only used for simulated targets, on real targets a fixed location VSR
## table is now allocated at 0x80000100.
 
#ifndef CYG_HAL_CALM32_VSR_TABLE_DEFINED
 
##      .section ".vsr_table","a"
 
        .data
 
        .globl  hal_vsr_table
hal_vsr_table:
        .long   __default_fiq_vsr       // FIQ
        .long   __default_irq_vsr       // IRQ
        .long   __default_exception_vsr // COP
        .long   __default_exception_vsr // DABRT
        .long   __default_exception_vsr // IABRT
        .long   __default_exception_vsr // PRIV
        .long   __default_exception_vsr // UNIMPL
        .long   __default_exception_vsr // TRACE
        .long   __default_swi_vsr       // SWI
#endif
 
        .balign 16
#ifdef CYGSEM_HAL_VIRTUAL_VECTOR_SUPPORT
        ## Vectors used to communicate between eCos and ROM environments
        .globl  hal_virtual_vector_table
hal_virtual_vector_table:
        .rept   64
        .long   0
        .endr
#endif
 
#------------------------------------------------------------------------------
# Interrupt vector tables.
# These tables contain the isr, data and object pointers used to deliver
# interrupts to user code.
# hal_interrupt_level contains the interrupt level set by
# HAL_INTERRUPT_CONFIGURE().
# This is a default set that provide support only for the single external
# interrupt. Platforms or boards are expected to define their own versions
# of these if they have their own interrupt mappings.
 
#ifndef CYG_HAL_CALM32_ISR_TABLES_DEFINED
 
        .extern hal_default_isr
 
        .data
 
        .globl  hal_interrupt_handlers
hal_interrupt_handlers:
        .long   hal_default_isr
        .long   hal_default_isr
 
 
        .globl  hal_interrupt_data
hal_interrupt_data:
        .long   0
        .long   0
 
        .globl  hal_interrupt_objects
hal_interrupt_objects:
        .long   0
        .long   0
#endif
 
        .data
        .globl __break_inst_in_data
__break_inst_in_data:
        .short 0x80e0
 
 
##-----------------------------------------------------------------------------
## end of vectors.S
 
 

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[/] [openrisc/] [trunk/] [rtos/] [ecos-2.0/] [packages/] [hal/] [calmrisc32/] [arch/] [v2_0/] [src/] [vectors.S] - Blame information for rev 565

Line No.	Rev	Author	Line
1	27	unneback	`##=============================================================================`
2			`##`
3			`## vectors.S`
4			`##`
5			`## CalmRISC32 exception vectors`
6			`##`
7			`##=============================================================================`
8			`#####ECOSGPLCOPYRIGHTBEGIN####`
9			`## -------------------------------------------`
10			`## This file is part of eCos, the Embedded Configurable Operating System.`
11			`## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.`
12			`##`
13			`## eCos is free software; you can redistribute it and/or modify it under`
14			`## the terms of the GNU General Public License as published by the Free`
15			`## Software Foundation; either version 2 or (at your option) any later version.`
16			`##`
17			`## eCos is distributed in the hope that it will be useful, but WITHOUT ANY`
18			`## WARRANTY; without even the implied warranty of MERCHANTABILITY or`
19			`## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License`
20			`## for more details.`
21			`##`
22			`## You should have received a copy of the GNU General Public License along`
23			`## with eCos; if not, write to the Free Software Foundation, Inc.,`
24			`## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.`
25			`##`
26			`## As a special exception, if other files instantiate templates or use macros`
27			`## or inline functions from this file, or you compile this file and link it`
28			`## with other works to produce a work based on this file, this file does not`
29			`## by itself cause the resulting work to be covered by the GNU General Public`
30			`## License. However the source code for this file must still be made available`
31			`## in accordance with section (3) of the GNU General Public License.`
32			`##`
33			`## This exception does not invalidate any other reasons why a work based on`
34			`## this file might be covered by the GNU General Public License.`
35			`##`
36			`## Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.`
37			`## at http://sources.redhat.com/ecos/ecos-license/`
38			`## -------------------------------------------`
39			`#####ECOSGPLCOPYRIGHTEND####`
40			`##=============================================================================`
41			`#######DESCRIPTIONBEGIN####`
42			`##`
43			`## Author(s): msalter`
44			`## Contributors: msalter`
45			`## Date: 2001-02-12`
46			`## Purpose: CalmRISC32 exception vectors`
47			`## Description: This file defines the code placed into the exception`
48			`## vectors. It also contains the first level default VSRs`
49			`## that save and restore state for both exceptions and`
50			`## interrupts.`
51			`##`
52			`######DESCRIPTIONEND####`
53			`##`
54			`##=============================================================================`
55
56			`#include`
57			`#include`
58			`#include`
59
60			`#ifdef CYGPKG_KERNEL`
61			`# include`
62			`#else`
63			`# undef CYGFUN_HAL_COMMON_KERNEL_SUPPORT`
64			`# undef CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK`
65			`#endif`
66
67			`#include`
68			`#include`
69
70			`.macro txreg reg`
71			`99:`
72			`cld r0,fr29`
73			`cmp eq r0,#0`
74			`brfd 99b`
75			`nop`
76			`cld fr30,\reg`
77			`ld r0,#1`
78			`cld fr29,r0`
79			`.endm`
80
81			`.extern cyg_instrument`
82
83			`##-----------------------------------------------------------------------------`
84			`## Hardware supplied vectors`
85
86			`.macro cpu_vector vsr_nr`
87			`setsr bs`
88			`clrsr rs0`
89			`clrsr rs1`
90			`nop`
91			`push r8`
92			`brad __exc_trampoline`
93			`ld r8,#\vsr_nr`
94			`.endm`
95
96			`##==========================================================================`
97			`## Hardware exception vectors.`
98			`##`
99			`.section ".vectors","ax"`
100			`.global reset_vector`
101			`reset_vector:`
102			`ldw r0,#_start`
103			`jmpd r0`
104			`nop`
105
106			`# 0x20 - FIQ`
107			`.p2align 5`
108			`cpu_vector 0`
109
110			`# 0x40 - IRQ`
111			`.p2align 5`
112			`cpu_vector 1`
113
114			`# 0x50 - COP`
115			`.p2align 4`
116			`cpu_vector 2`
117
118			`# 0x60 - DABRT`
119			`.p2align 4`
120			`cpu_vector 3`
121
122			`# 0x70 - IABRT`
123			`.p2align 4`
124			`cpu_vector 4`
125
126			`# 0x80 - PRIV`
127			`.p2align 4`
128			`cpu_vector 5`
129
130			`# 0xA0 - UNIMPL`
131			`.p2align 5`
132			`cpu_vector 6`
133
134			`# 0xC0 - TRACE`
135			`.p2align 5`
136			`cpu_vector 7`
137
138			`# 0x100 - SWI 0`
139			`.p2align 6`
140			`cpu_vector 8`
141
142			`# SWI 1`
143			`.p2align 4`
144			`cpu_vector 8`
145
146			`# SWI 2`
147			`.p2align 4`
148			`cpu_vector 8`
149
150			`# SWI 3`
151			`.p2align 4`
152			`cpu_vector 8`
153
154			`# SWI 4`
155			`.p2align 4`
156			`cpu_vector 8`
157
158			`# SWI 5`
159			`.p2align 4`
160			`cpu_vector 8`
161
162			`# SWI 6`
163			`.p2align 4`
164			`cpu_vector 8`
165
166			`# SWI 7`
167			`.p2align 4`
168			`cpu_vector 8`
169
170			`# SWI 8`
171			`.p2align 4`
172			`cpu_vector 8`
173
174			`# SWI 9`
175			`.p2align 4`
176			`cpu_vector 8`
177
178			`# SWI 10`
179			`.p2align 4`
180			`cpu_vector 8`
181
182			`# SWI 11`
183			`.p2align 4`
184			`cpu_vector 8`
185
186			`# SWI 12`
187			`.p2align 4`
188			`cpu_vector 8`
189
190			`# SWI 13`
191			`.p2align 4`
192			`cpu_vector 8`
193
194			`# SWI 14`
195			`.p2align 4`
196			`cpu_vector 8`
197
198			`# SWI 15`
199			`.p2align 4`
200			`cpu_vector 8`
201
202			`__exc_trampoline:`
203			`push r8 // vsr number`
204			`sl2 r8 // offset into vsr table`
205			`ldw r8,@[r8 + 0]`
206			`jmpd r8`
207			`pop r8`
208
209			`##-----------------------------------------------------------------------------`
210			`## Startup code`
211
212			`.text`
213
214			`FUNC_START _start`
215			`# default vector table`
216			`ld r0,#0`
217			`ld vbr,r0`
218
219			`# ensure privileged mode with all bank1 register view`
220			`setsr pm`
221			`setsr bs`
222			`clrsr rs0`
223			`clrsr rs1`
224
225			`# Initialize hardware`
226			`hal_cpu_init`
227			`hal_diag_init`
228			`hal_memc_init`
229			`hal_cache_init`
230			`hal_timer_init`
231
232			`# load initial stack pointer`
233			`ldw sp,#__startup_stack`
234
235			`clrsr bs`
236			`nop`
237			`ldw sp,#__user_stack`
238			`setsr bs`
239			`nop`
240
241			`hal_mon_init`
242
243			`#ifdef CYG_HAL_STARTUP_ROM`
244			`# Copy data from ROM to RAM`
245
246			`.extern hal_copy_data`
247			`ldw r0,#hal_copy_data`
248			`jsrd r0`
249			`nop`
250			`#endif`
251
252			`# Zero BSS`
253
254			`.extern hal_zero_bss`
255			`ldw r0,#hal_zero_bss`
256			`jsrd r0`
257			`nop`
258
259			`# Call variant and platform HAL`
260			`# initialization routines.`
261
262			`.extern hal_variant_init`
263			`ldw r0,#hal_variant_init`
264			`jsrd r0`
265			`nop`
266
267			`.extern hal_platform_init`
268			`ldw r0,#hal_platform_init`
269			`jsrd r0`
270			`nop`
271
272			`# Call constructors`
273			`.extern cyg_hal_invoke_constructors`
274			`ldw r0,#cyg_hal_invoke_constructors`
275			`jsrd r0`
276			`nop`
277
278			`#if defined(CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS)`
279			`.extern initialize_stub`
280			`ldw r0,#initialize_stub`
281			`jsrd r0`
282			`nop`
283			`#endif`
284
285			`#if defined(CYGDBG_HAL_CALM32_DEBUG_GDB_CTRLC_SUPPORT)`
286			`.extern hal_ctrlc_isr_init`
287			`ldw r0,#hal_ctrlc_isr_init`
288			`jsrd r0`
289			`nop`
290			`#endif`
291
292			`# Call cyg_start`
293
294			`.extern cyg_start`
295			`#if 0`
296			`clrsr pm`
297			`nop`
298			`clrsr bs`
299			`nop`
300			`#endif`
301			`ld fp,sp`
302
303			`ldw lr,#_start`
304			`ldw r0,#cyg_start`
305			`jmpd r0`
306			`nop`
307			`FUNC_END _start`
308
309
310			`.macro switch_stack_and_save_regs tmpvar`
311			`// save vector number temporarily`
312			`push r9`
313			`ldw r9,#\tmpvar`
314			`ldw @[r9 + 0],r8`
315			`pop r9`
316
317			`// Make sure we use the gdb stack`
318			`ldw r8,#__GDB_stack`
319			`cmpu gt sp,r8`
320			`brtd 0f`
321			`nop`
322			`ldw r8,#__GDB_stack_base`
323			`cmpu gt sp,r8`
324			`brtd 1f`
325			`nop`
326			`0:`
327			`// need to switch stack`
328			`ld r8,sp`
329			`add r8,#4`
330			`ldw sp,#__GDB_stack`
331			`push r8`
332			`push r14`
333			`push r13`
334			`push r12`
335			`sub r8,#4`
336			`brad 2f`
337			`ldw r8,@[r8+0]`
338			`1:`
339			`// already using gdb stack`
340			`pop r8`
341			`// save bank 1 regs`
342			`push q3`
343			`2:`
344			`// save rest of bank1 regs`
345			`push q2`
346			`push q1`
347			`push q0`
348
349			`// save bank 0 regs`
350			`setsr rs1`
351			`nop`
352			`push q1`
353			`push q0`
354			`clrsr rs1`
355			`setsr rs0`
356			`nop`
357			`push q1`
358			`push q0`
359			`clrsr rs0`
360			`nop`
361			`// save special regs`
362			`ld r0,ssr_expt`
363			`push r0`
364			`ld r0,ssr_swi`
365			`push r0`
366			`ld r0,ssr_fiq`
367			`push r0`
368			`ld r0,ssr_irq`
369			`push r0`
370			`ld r0,spc_expt`
371			`push r0`
372			`ld r0,spc_swi`
373			`push r0`
374			`ld r0,spc_fiq`
375			`push r0`
376			`ld r0,spc_irq`
377			`push r0`
378			`ld r0,vbr`
379			`push r0`
380
381			`ldw r8,#\tmpvar`
382			`ldw r8,@[r8+0]`
383			`push r8`
384			`.endm`
385
386			`.macro restore_regs`
387			`// discard vector`
388			`pop r0`
389			`// restore special regs`
390			`pop r0`
391			`ld vbr,r0`
392			`pop r0`
393			`ld spc_irq,r0`
394			`pop r0`
395			`ld spc_fiq,r0`
396			`pop r0`
397			`ld spc_swi,r0`
398			`pop r0`
399			`ld spc_expt,r0`
400			`pop r0`
401			`ld ssr_irq,r0`
402			`pop r0`
403			`ld ssr_fiq,r0`
404			`pop r0`
405			`ld ssr_swi,r0`
406			`pop r0`
407			`ld ssr_expt,r0`
408			`// restore bank 0 regs`
409			`setsr rs1`
410			`nop`
411			`pop q0`
412			`pop q1`
413			`clrsr rs1`
414			`setsr rs0`
415			`nop`
416			`pop q0`
417			`pop q1`
418			`clrsr rs0`
419			`nop`
420			`// restore bank 1 regs`
421			`pop q0`
422			`pop q1`
423			`pop q2`
424			`pop q3`
425			`.endm`
426
427
428			`##-----------------------------------------------------------------------------`
429			`## Default exception VSR.`
430			`## Saves machine state and calls external handling code.`
431			`## On entry, the original R8 has been pushed on the stack and R8 now`
432			`## contains the vector number.`
433
434			`FUNC_START __default_exception_vsr`
435
436			`switch_stack_and_save_regs __expt_temp`
437
438			`// call exception handler`
439			`ldw r8,#cyg_hal_exception_handler`
440			`jsrd r8`
441			`ld r0,sp`
442
443			`restore_regs`
444
445			`ret_expt`
446			`nop`
447
448			`FUNC_END __default_exception_vsr`
449
450			`##-----------------------------------------------------------------------------`
451			`## Default swi VSR.`
452			`## Saves machine state and calls external handling code.`
453			`## On entry, the original R8 has been pushed on the stack and R8 now`
454			`## contains the vector number.`
455
456			`FUNC_START __default_swi_vsr`
457
458			`switch_stack_and_save_regs __swi_temp`
459
460			`// call exception handler`
461			`ldw r8,#cyg_hal_exception_handler`
462			`jsrd r8`
463			`ld r0,sp`
464
465			`restore_regs`
466
467			`ret_swi`
468			`nop`
469
470			`FUNC_END __default_swi_vsr`
471
472			`##------------------------------------------------------------------------------`
473			`## Default interrupt VSR.`
474			`## Saves machine state and calls appropriate ISR. When done, calls`
475			`## interrupt_end() to finish up and possibly reschedule.`
476
477			`FUNC_START __default_fiq_vsr`
478			`switch_stack_and_save_regs __fiq_temp`
479
480			`ldw r8,#hal_interrupt_data`
481			`ldw r1,@[r8 + 0]`
482			`ldw r8,#hal_interrupt_handlers`
483			`ldw r8,@[r8 + 0]`
484
485			`// call fiq handler`
486			`jsrd r8`
487			`ld r0,#0`
488
489			`restore_regs`
490
491			`ret_fiq`
492			`nop`
493			`FUNC_END __default_fiq_vsr`
494
495			`FUNC_START __default_irq_vsr`
496			`switch_stack_and_save_regs __irq_temp`
497
498			`ldw r8,#hal_interrupt_data`
499			`ldw r1,@[r8 + 4]`
500			`ldw r8,#hal_interrupt_handlers`
501			`ldw r8,@[r8 + 4]`
502
503			`// call fiq handler`
504			`jsrd r8`
505			`ld r0,#1`
506
507			`restore_regs`
508
509			`ret_irq`
510			`nop`
511			`FUNC_END __default_irq_vsr`
512
513			`##-----------------------------------------------------------------------------`
514			`## Execute pending DSRs on the interrupt stack with interrupts enabled.`
515			`## Note: this can only be called from code running on a thread stack`
516
517			`#ifdef CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK`
518			`.extern cyg_interrupt_call_pending_DSRs`
519
520			`FUNC_START hal_interrupt_stack_call_pending_DSRs`
521			`FUNC_END hal_interrupt_stack_call_pending_DSRs`
522			`#endif`
523
524			`##-----------------------------------------------------------------------------`
525			`## Short circuit in case any code tries to use "__gccmain()"`
526
527			`FUNC_START __gccmain`
528			`jmpd lr`
529			`nop`
530			`FUNC_END __gccmain`
531
532			`##-----------------------------------------------------------------------------`
533			`## Interrupt Stack.`
534			`## Used during intialization and for executing ISRs.`
535
536			`.section ".bss"`
537
538			`.balign 16`
539			`.global cyg_interrupt_stack_base`
540			`cyg_interrupt_stack_base:`
541			`__interrupt_stack_base:`
542			`.rept CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE`
543			`.byte 0`
544			`.endr`
545			`.balign 16`
546			`.global cyg_interrupt_stack`
547			`cyg_interrupt_stack:`
548			`__interrupt_stack:`
549
550			`.long 0`
551
552			`#ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS`
553			`.balign 16`
554			`__GDB_stack_base:`
555			`.rept 0x400`
556			`.byte 0`
557			`.endr`
558			`__GDB_stack:`
559			`.long 0`
560			`#endif`
561			`.balign 16`
562			`__startup_stack_base:`
563			`#ifdef CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK`
564			`.rept 512`
565			`#else`
566			`.rept CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE`
567			`#endif`
568			`.byte 0`
569			`.endr`
570			`.balign 16`
571			`__startup_stack:`
572			`.long 0`
573
574			`.balign 16`
575			`__user_stack_base:`
576			`#ifdef CYGIMP_HAL_COMMON_INTERRUPTS_USE_INTERRUPT_STACK`
577			`.rept 512`
578			`#else`
579			`.rept CYGNUM_HAL_COMMON_INTERRUPTS_STACK_SIZE`
580			`#endif`
581			`.byte 0`
582			`.endr`
583			`.balign 16`
584			`__user_stack:`
585			`.long 0`
586
587			`__expt_temp:`
588			`.long 0`
589			`__swi_temp:`
590			`.long 0`
591			`__irq_temp:`
592			`.long 0`
593			`__fiq_temp:`
594			`.long 0`
595
596
597			`##-----------------------------------------------------------------------------`
598			`## VSR table.`
599			`## The main interrupt code indirects through here to find the VSR`
600			`## to execute for each architecture defined interrupt.`
601			`## This is only used for simulated targets, on real targets a fixed location VSR`
602			`## table is now allocated at 0x80000100.`
603
604			`#ifndef CYG_HAL_CALM32_VSR_TABLE_DEFINED`
605
606			`## .section ".vsr_table","a"`
607
608			`.data`
609
610			`.globl hal_vsr_table`
611			`hal_vsr_table:`
612			`.long __default_fiq_vsr // FIQ`
613			`.long __default_irq_vsr // IRQ`
614			`.long __default_exception_vsr // COP`
615			`.long __default_exception_vsr // DABRT`
616			`.long __default_exception_vsr // IABRT`
617			`.long __default_exception_vsr // PRIV`
618			`.long __default_exception_vsr // UNIMPL`
619			`.long __default_exception_vsr // TRACE`
620			`.long __default_swi_vsr // SWI`
621			`#endif`
622
623			`.balign 16`
624			`#ifdef CYGSEM_HAL_VIRTUAL_VECTOR_SUPPORT`
625			`## Vectors used to communicate between eCos and ROM environments`
626			`.globl hal_virtual_vector_table`
627			`hal_virtual_vector_table:`
628			`.rept 64`
629			`.long 0`
630			`.endr`
631			`#endif`
632
633			`#------------------------------------------------------------------------------`
634			`# Interrupt vector tables.`
635			`# These tables contain the isr, data and object pointers used to deliver`
636			`# interrupts to user code.`
637			`# hal_interrupt_level contains the interrupt level set by`
638			`# HAL_INTERRUPT_CONFIGURE().`
639			`# This is a default set that provide support only for the single external`
640			`# interrupt. Platforms or boards are expected to define their own versions`
641			`# of these if they have their own interrupt mappings.`
642
643			`#ifndef CYG_HAL_CALM32_ISR_TABLES_DEFINED`
644
645			`.extern hal_default_isr`
646
647			`.data`
648
649			`.globl hal_interrupt_handlers`
650			`hal_interrupt_handlers:`
651			`.long hal_default_isr`
652			`.long hal_default_isr`
653
654
655			`.globl hal_interrupt_data`
656			`hal_interrupt_data:`
657			`.long 0`
658			`.long 0`
659
660			`.globl hal_interrupt_objects`
661			`hal_interrupt_objects:`
662			`.long 0`
663			`.long 0`
664			`#endif`
665
666			`.data`
667			`.globl __break_inst_in_data`
668			`__break_inst_in_data:`
669			`.short 0x80e0`
670
671
672			`##-----------------------------------------------------------------------------`
673			`## end of vectors.S`
674
675