OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [rtos/] [ecos-2.0/] [packages/] [hal/] [common/] [v2_0/] [tests/] [intr.c] - Blame information for rev 279

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 27 unneback
/*=================================================================
2
//
3
//        intr.c
4
//
5
//        HAL Interrupt API test
6
//
7
//==========================================================================
8
//####ECOSGPLCOPYRIGHTBEGIN####
9
// -------------------------------------------
10
// This file is part of eCos, the Embedded Configurable Operating System.
11
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
12
//
13
// eCos is free software; you can redistribute it and/or modify it under
14
// the terms of the GNU General Public License as published by the Free
15
// Software Foundation; either version 2 or (at your option) any later version.
16
//
17
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
18
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
19
// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
20
// for more details.
21
//
22
// You should have received a copy of the GNU General Public License along
23
// with eCos; if not, write to the Free Software Foundation, Inc.,
24
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
25
//
26
// As a special exception, if other files instantiate templates or use macros
27
// or inline functions from this file, or you compile this file and link it
28
// with other works to produce a work based on this file, this file does not
29
// by itself cause the resulting work to be covered by the GNU General Public
30
// License. However the source code for this file must still be made available
31
// in accordance with section (3) of the GNU General Public License.
32
//
33
// This exception does not invalidate any other reasons why a work based on
34
// this file might be covered by the GNU General Public License.
35
//
36
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
37
// at http://sources.redhat.com/ecos/ecos-license/
38
// -------------------------------------------
39
//####ECOSGPLCOPYRIGHTEND####
40
//==========================================================================
41
//#####DESCRIPTIONBEGIN####
42
//
43
// Author(s):     nickg
44
// Contributors:  nickg
45
// Date:          1998-10-08
46
//####DESCRIPTIONEND####
47
*/
48
 
49
#include <pkgconf/hal.h>
50
 
51
#include <cyg/infra/testcase.h>
52
 
53
#include <cyg/hal/hal_intr.h>
54
#include <cyg/hal/drv_api.h>
55
 
56
// Include HAL/Platform specifics
57
#include CYGBLD_HAL_PLATFORM_H
58
 
59
#ifdef CYGPKG_KERNEL
60
#include <pkgconf/kernel.h>             // Need to look for the RTC config.
61
#endif
62
 
63
// Fallback defaults (in case HAL didn't define these)
64
#ifndef CYGNUM_HAL_RTC_NUMERATOR       
65
#define CYGNUM_HAL_RTC_NUMERATOR     1000000000
66
#define CYGNUM_HAL_RTC_DENOMINATOR   100
67
#define CYGNUM_HAL_RTC_PERIOD        9999
68
#endif
69
 
70
// -------------------------------------------------------------------------
71
 
72
#define ISR_DATA        0xAAAA1234
73
 
74
// -------------------------------------------------------------------------
75
 
76
volatile cyg_count32 ticks = 0;
77
static cyg_interrupt intr;
78
static cyg_handle_t  intr_handle;
79
 
80
// -------------------------------------------------------------------------
81
 
82
cyg_uint32 isr( cyg_uint32 vector, CYG_ADDRWORD data )
83
{
84
    CYG_TEST_CHECK( ISR_DATA == data , "Bad data passed to ISR");
85
    CYG_TEST_CHECK( CYGNUM_HAL_INTERRUPT_RTC == vector ,
86
                    "Bad vector passed to ISR");
87
 
88
    HAL_CLOCK_RESET( vector, CYGNUM_HAL_RTC_PERIOD );
89
 
90
    HAL_INTERRUPT_ACKNOWLEDGE( vector );
91
 
92
    ticks++;
93
 
94
    return CYG_ISR_HANDLED;
95
}
96
 
97
// -------------------------------------------------------------------------
98
 
99
 
100
void intr_main( void )
101
{
102
    CYG_INTERRUPT_STATE oldints;
103
 
104
    cyg_drv_interrupt_create(CYGNUM_HAL_INTERRUPT_RTC, 1,
105
                             ISR_DATA, isr, NULL, &intr_handle, &intr);
106
    cyg_drv_interrupt_attach(intr_handle);
107
    HAL_CLOCK_INITIALIZE( CYGNUM_HAL_RTC_PERIOD );
108
    cyg_drv_interrupt_unmask(CYGNUM_HAL_INTERRUPT_RTC);
109
 
110
    HAL_ENABLE_INTERRUPTS();
111
 
112
    while( ticks < 10 )
113
    {
114
 
115
    }
116
 
117
    HAL_DISABLE_INTERRUPTS(oldints);
118
 
119
    CYG_TEST_PASS_FINISH("HAL interrupt test");
120
}
121
 
122
 
123
// -------------------------------------------------------------------------
124
 
125
externC void
126
cyg_start( void )
127
{
128
    CYG_TEST_INIT();
129
 
130
    // Attaching the ISR will not succeed if the kernel real-time
131
    // clock has been configured in.
132
#ifndef CYGVAR_KERNEL_COUNTERS_CLOCK
133
 
134
    intr_main();
135
 
136
#else
137
 
138
    CYG_TEST_NA("Cannot override kernel real-time clock.");
139
 
140
#endif
141
}
142
 
143
 
144
// -------------------------------------------------------------------------
145
// EOF intr.c

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.