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#ifndef CYGONCE_HAL_CACHE_H
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#define CYGONCE_HAL_CACHE_H
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//=============================================================================
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//
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// hal_cache.h
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//
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// HAL cache control API
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//
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//=============================================================================
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//####ECOSGPLCOPYRIGHTBEGIN####
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// -------------------------------------------
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// This file is part of eCos, the Embedded Configurable Operating System.
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// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
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//
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// eCos is free software; you can redistribute it and/or modify it under
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// the terms of the GNU General Public License as published by the Free
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// Software Foundation; either version 2 or (at your option) any later version.
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//
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// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// for more details.
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//
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// You should have received a copy of the GNU General Public License along
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// with eCos; if not, write to the Free Software Foundation, Inc.,
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// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
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//
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// As a special exception, if other files instantiate templates or use macros
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// or inline functions from this file, or you compile this file and link it
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// with other works to produce a work based on this file, this file does not
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// by itself cause the resulting work to be covered by the GNU General Public
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// License. However the source code for this file must still be made available
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// in accordance with section (3) of the GNU General Public License.
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//
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// This exception does not invalidate any other reasons why a work based on
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// this file might be covered by the GNU General Public License.
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//
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// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
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// at http://sources.redhat.com/ecos/ecos-license/
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// -------------------------------------------
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//####ECOSGPLCOPYRIGHTEND####
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//=============================================================================
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//#####DESCRIPTIONBEGIN####
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//
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// Author(s): gthomas
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// Contributors:hmt
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// Date: 2000-05-08
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// Purpose: Cache control API
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// Description: The macros defined here provide the HAL APIs for handling
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// cache control operations.
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// Usage:
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// #include <cyg/hal/hal_cache.h>
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// ...
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//
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//
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//####DESCRIPTIONEND####
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//
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//=============================================================================
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#include <cyg/infra/cyg_type.h>
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#include CYGBLD_HAL_PLF_DEFS_H
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#include <cyg/hal/plf_cache.h> // Platform (model) details
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//-----------------------------------------------------------------------------
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// Global control of Instruction cache
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// Enable the instruction cache
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#define HAL_ICACHE_ENABLE() \
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CYG_MACRO_START \
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cyg_uint32 mask = _HSR0_ICE; \
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asm volatile ( \
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"movsg hsr0,gr4\n" \
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"\tor gr4,%0,gr4\n" \
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"\tmovgs gr4,hsr0\n" \
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: \
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: "r"(mask) \
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: "gr4" /* Clobber list */ \
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); \
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CYG_MACRO_END
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// Disable the instruction cache (and invalidate it, required semanitcs)
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#define HAL_ICACHE_DISABLE() \
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CYG_MACRO_START \
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cyg_uint32 mask = ~_HSR0_ICE; \
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asm volatile ( \
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"movsg hsr0,gr4\n" \
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"\tand gr4,%0,gr4\n" \
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"\tmovgs gr4,hsr0\n" \
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: \
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: "r"(mask) \
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: "gr4" /* Clobber list */ \
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); \
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CYG_MACRO_END
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// Query the state of the instruction cache
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#define HAL_ICACHE_IS_ENABLED(_state_) \
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CYG_MACRO_START \
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register cyg_uint32 reg; \
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asm volatile ("movsg hsr0,%0" \
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: "=r"(reg) \
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: \
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); \
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(_state_) = (0 != (_HSR0_ICE & reg)); \
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CYG_MACRO_END
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// Invalidate the entire cache
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#define HAL_ICACHE_INVALIDATE_ALL() \
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CYG_MACRO_START \
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asm volatile ("icei @(gr4,gr0),1" \
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: \
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: \
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); \
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CYG_MACRO_END
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// Synchronize the contents of the cache with memory.
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// (which includes flushing out pending writes)
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#define HAL_ICACHE_SYNC() \
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CYG_MACRO_START \
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HAL_DCACHE_SYNC(); /* ensure data gets to RAM */ \
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HAL_ICACHE_INVALIDATE_ALL(); /* forget all we know */ \
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CYG_MACRO_END
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// Set the instruction cache refill burst size
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//#define HAL_ICACHE_BURST_SIZE(_size_)
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// Load the contents of the given address range into the instruction cache
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// and then lock the cache so that it stays there.
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//#define HAL_ICACHE_LOCK(_base_, _size_)
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// Undo a previous lock operation
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//#define HAL_ICACHE_UNLOCK(_base_, _size_)
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// Unlock entire cache
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//#define HAL_ICACHE_UNLOCK_ALL()
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//-----------------------------------------------------------------------------
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// Instruction cache line control
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// Invalidate cache lines in the given range without writing to memory.
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#define HAL_ICACHE_INVALIDATE( _base_ , _size_ ) \
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CYG_MACRO_START \
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cyg_uint32 _b = _base_; \
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cyg_uint32 _s = _size_; \
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while (_s > HAL_DCACHE_LINE_SIZE) { \
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asm volatile ("ici @(%0,gr0)" \
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: \
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: "r"(_b) \
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); \
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_s -= HAL_DCACHE_LINE_SIZE; \
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_b += HAL_DCACHE_LINE_SIZE; \
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} \
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CYG_MACRO_END
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//-----------------------------------------------------------------------------
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// Global control of data cache
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// Enable the data cache
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#define HAL_DCACHE_ENABLE() \
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CYG_MACRO_START \
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cyg_uint32 mask = _HSR0_DCE; \
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asm volatile ( \
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"movsg hsr0,gr4\n" \
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"\tor gr4,%0,gr4\n" \
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"\tmovgs gr4,hsr0\n" \
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: \
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: "r"(mask) \
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: "gr4" /* Clobber list */ \
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); \
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CYG_MACRO_END
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// Disable the data cache (and invalidate it, required semanitcs)
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#define HAL_DCACHE_DISABLE() \
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CYG_MACRO_START \
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cyg_uint32 mask = ~_HSR0_DCE; \
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asm volatile ( \
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"movsg hsr0,gr4\n" \
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"\tand gr4,%0,gr4\n" \
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"\tmovgs gr4,hsr0\n" \
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: \
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: "r"(mask) \
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: "gr4" /* Clobber list */ \
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); \
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CYG_MACRO_END
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// Query the state of the data cache
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#define HAL_DCACHE_IS_ENABLED(_state_) \
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CYG_MACRO_START \
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register cyg_uint32 reg; \
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asm volatile ("movsg hsr0,%0" \
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: "=r"(reg) \
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: \
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); \
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(_state_) = (0 != (_HSR0_DCE & reg)); \
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CYG_MACRO_END
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// Flush (invalidate) the entire dcache
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#define HAL_DCACHE_INVALIDATE_ALL() \
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CYG_MACRO_START \
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asm volatile ("dcei @(gr4,gr0),1" \
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: \
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: \
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); \
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CYG_MACRO_END
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// Synchronize the contents of the cache with memory.
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#define HAL_DCACHE_SYNC() \
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CYG_MACRO_START \
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asm volatile ("dcef @(gr4,gr0),1" \
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: \
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: \
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); \
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CYG_MACRO_END
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// Set the data cache refill burst size
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//#define HAL_DCACHE_BURST_SIZE(_size_)
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// Set the data cache write mode
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//#define HAL_DCACHE_WRITE_MODE( _mode_ )
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#define HAL_DCACHE_WRITETHRU_MODE 0
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#define HAL_DCACHE_WRITEBACK_MODE 1
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// Get the current writeback mode - or only writeback mode if fixed
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#define HAL_DCACHE_QUERY_WRITE_MODE( _mode_ ) CYG_MACRO_START \
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_mode_ = HAL_DCACHE_WRITETHRU_MODE; \
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CYG_MACRO_END
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// Load the contents of the given address range into the data cache
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// and then lock the cache so that it stays there.
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//#define HAL_DCACHE_LOCK(_base_, _size_)
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// Undo a previous lock operation
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//#define HAL_DCACHE_UNLOCK(_base_, _size_)
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// Unlock entire cache
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//#define HAL_DCACHE_UNLOCK_ALL()
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//-----------------------------------------------------------------------------
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// Data cache line control
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// Allocate cache lines for the given address range without reading its
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// contents from memory.
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//#define HAL_DCACHE_ALLOCATE( _base_ , _size_ )
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// Write dirty cache lines to memory and invalidate the cache entries
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// for the given address range.
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#define HAL_DCACHE_FLUSH( _base_ , _size_ ) \
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CYG_MACRO_START \
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HAL_DCACHE_STORE( _base_ , _size_ ); \
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HAL_DCACHE_INVALIDATE( _base_ , _size_ ); \
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CYG_MACRO_END
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// Invalidate cache lines in the given range without writing to memory.
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#define HAL_DCACHE_INVALIDATE( _base_ , _size_ ) \
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CYG_MACRO_START \
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cyg_uint32 _b = _base_; \
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cyg_uint32 _s = _size_; \
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while (_s > HAL_DCACHE_LINE_SIZE) { \
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asm volatile ("dci @(%0,gr0)" \
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: \
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: "r"(_b) \
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); \
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_s -= HAL_DCACHE_LINE_SIZE; \
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_b += HAL_DCACHE_LINE_SIZE; \
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} \
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CYG_MACRO_END
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// Write dirty cache lines to memory for the given address range.
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#define HAL_DCACHE_STORE( _base_ , _size_ ) \
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CYG_MACRO_START \
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cyg_uint32 _b = _base_; \
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cyg_uint32 _s = _size_; \
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while (_s > HAL_DCACHE_LINE_SIZE) { \
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asm volatile ("dcf @(%0,gr0)" \
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: \
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: "r"(_b) \
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); \
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_s -= HAL_DCACHE_LINE_SIZE; \
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_b += HAL_DCACHE_LINE_SIZE; \
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} \
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CYG_MACRO_END
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// Preread the given range into the cache with the intention of reading
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// from it later.
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//#define HAL_DCACHE_READ_HINT( _base_ , _size_ )
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// Preread the given range into the cache with the intention of writing
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// to it later.
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//#define HAL_DCACHE_WRITE_HINT( _base_ , _size_ )
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// Allocate and zero the cache lines associated with the given range.
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//#define HAL_DCACHE_ZERO( _base_ , _size_ )
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//-----------------------------------------------------------------------------
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#endif // ifndef CYGONCE_HAL_CACHE_H
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// End of hal_cache.h
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