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# ====================================================================

#

#      hal_h8300_h8300h.cdl

#

#      H8/300H variant architectural HAL package configuration data

#

# ====================================================================

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# ====================================================================

######DESCRIPTIONBEGIN####

#

# Author(s):      jskov

# Original data:  nickg

# Contributors:   dmoseley

# Date:           1999-11-02

#

#####DESCRIPTIONEND####

#

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cdl_package CYGPKG_HAL_H8300_H8300H {

    display "H8/300H variant"

    parent        CYGPKG_HAL_H8300

    implements CYGINT_HAL_H8300_VARIANT

    hardware

    include_dir   cyg/hal

    define_header hal_h8300_h8300h.h

    description   "

           The H8/300H variant HAL package provides generic

           support for this processor architecture. It is also

           necessary to select a specific target platform HAL

           package."

    define_proc {

        puts $::cdl_header "#include "

    }

    compile       var_misc.c h8_sci.c

    make {

        /lib/target.ld: /src/h8300_h8300h.ld

        $(CC) -E -P -Wp,-MD,target.tmp -DEXTRAS=1 -xc $(INCLUDE_PATH) $(CFLAGS) -o $@ $<

        @echo $@ ": \\" > $(notdir $@).deps

        @tail +2 target.tmp >> $(notdir $@).deps

        @echo >> $(notdir $@).deps

        @rm target.tmp

    }

    cdl_option CYGBLD_LINKER_SCRIPT {

        display "Linker script"

        flavor data

        no_define

        calculated  { "src/h8300_h8300h.ld" }

    }

    cdl_component CYGHWR_HAL_H8300H_CLOCK_SETTINGS {

        display          "H8/300H on-chip generic clock controls"

        description      "

            The various clocks used by the system are controlled by

            these options, some of which are derived from platform

            settings."

        flavor        none

        no_define

        cdl_option CYGHWR_HAL_H8300_DIVIDER_RATE {

            display          "Divider Rate (1/n)"

            flavor           data

             legal_values     { 1 2 4 8 }

            default_value    1

            description      "

               The system clock divide rate setting"

        }

         cdl_option CYGHWR_HAL_H8300_PROCESSOR_SPEED {

             display          "Processor clock speed (MHz)"

             flavor           data

             calculated       { CYGHWR_HAL_H8300_CPG_INPUT / CYGHWR_HAL_H8300_DIVIDER_RATE }

             description      "

                 The core (CPU) speed is computed from

                 the input clock speed and the divider setting."

         }

    }

    cdl_option CYGNUM_HAL_H8300_H8300H_SCI_BAUD_RATE {

        display          "SCI serial port default baud rate"

        flavor data

        legal_values     { 4800 9600 14400 19200 38400 57600 115200 }

        default_value    { 38400 }

    }

}