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//==========================================================================
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//
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// var_misc.c
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//
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// HAL CPU variant miscellaneous functions
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//
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//==========================================================================
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//####ECOSGPLCOPYRIGHTBEGIN####
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// -------------------------------------------
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// This file is part of eCos, the Embedded Configurable Operating System.
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// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
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//
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// eCos is free software; you can redistribute it and/or modify it under
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// the terms of the GNU General Public License as published by the Free
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// Software Foundation; either version 2 or (at your option) any later version.
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//
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// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// for more details.
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//
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// You should have received a copy of the GNU General Public License along
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// with eCos; if not, write to the Free Software Foundation, Inc.,
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// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
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//
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// As a special exception, if other files instantiate templates or use macros
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// or inline functions from this file, or you compile this file and link it
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// with other works to produce a work based on this file, this file does not
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// by itself cause the resulting work to be covered by the GNU General Public
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// License. However the source code for this file must still be made available
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// in accordance with section (3) of the GNU General Public License.
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//
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// This exception does not invalidate any other reasons why a work based on
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// this file might be covered by the GNU General Public License.
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//
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// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
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// at http://sources.redhat.com/ecos/ecos-license/
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// -------------------------------------------
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//####ECOSGPLCOPYRIGHTEND####
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//==========================================================================
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//#####DESCRIPTIONBEGIN####
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//
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// Author(s): nickg
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// Contributors: nickg, jlarmour
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// Date: 1999-01-21
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// Purpose: HAL miscellaneous functions
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// Description: This file contains miscellaneous functions provided by the
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// HAL.
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//
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//####DESCRIPTIONEND####
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//
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//========================================================================*/
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#include <pkgconf/hal.h>
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#include <cyg/infra/cyg_type.h> // Base types
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#include <cyg/infra/cyg_trac.h> // tracing macros
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#include <cyg/infra/cyg_ass.h> // assertion macros
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#include <cyg/hal/var_arch.h>
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#include <cyg/hal/var_intr.h>
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#include <cyg/hal/hal_io.h>
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/*------------------------------------------------------------------------*/
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/* Variant specific initialization routine. */
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void hal_variant_init(void)
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{
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}
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struct int_regs {
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CYG_BYTE *ier;
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CYG_BYTE *isr;
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CYG_BYTE mask;
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CYG_BYTE status;
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};
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#define REGS_DEF(ier,isr,mask,status) \
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{(CYG_BYTE *)ier,(CYG_BYTE *)isr,mask,status}
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struct int_regs interrupt_registers[]= {
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REGS_DEF(CYGARC_IER,CYGARC_ISR,0x01,0x01),
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REGS_DEF(CYGARC_IER,CYGARC_ISR,0x02,0x02),
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REGS_DEF(CYGARC_IER,CYGARC_ISR,0x04,0x04),
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REGS_DEF(CYGARC_IER,CYGARC_ISR,0x08,0x08),
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REGS_DEF(CYGARC_IER,CYGARC_ISR,0x10,0x10),
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REGS_DEF(CYGARC_IER,CYGARC_ISR,0x20,0x20),
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REGS_DEF(CYGARC_IER,CYGARC_ISR,0x40,0x40),
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REGS_DEF(CYGARC_IER,CYGARC_ISR,0x80,0x80),
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REGS_DEF(CYGARC_TCSR,CYGARC_TCSR,0x20,0x80),
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REGS_DEF(CYGARC_RTMCSR,CYGARC_RTMCSR,0x40,0x80),
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REGS_DEF(NULL,NULL,0,0),
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REGS_DEF(CYGARC_ADCSR,CYGARC_ADCSR,0x40,0x80),
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REGS_DEF(CYGARC_TISRA,CYGARC_TISRA,0x10,0x01),
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REGS_DEF(CYGARC_TISRB,CYGARC_TISRB,0x10,0x01),
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REGS_DEF(CYGARC_TISRC,CYGARC_TISRC,0x10,0x01),
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REGS_DEF(NULL,NULL,0,0),
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REGS_DEF(CYGARC_TISRA,CYGARC_TISRA,0x20,0x02),
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REGS_DEF(CYGARC_TISRB,CYGARC_TISRB,0x20,0x02),
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REGS_DEF(CYGARC_TISRC,CYGARC_TISRC,0x20,0x02),
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REGS_DEF(NULL,NULL,0,0),
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REGS_DEF(CYGARC_TISRA,CYGARC_TISRA,0x40,0x04),
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REGS_DEF(CYGARC_TISRB,CYGARC_TISRB,0x40,0x04),
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REGS_DEF(CYGARC_TISRC,CYGARC_TISRC,0x40,0x04),
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REGS_DEF(NULL,NULL,0,0),
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REGS_DEF(CYGARC_8TCR0,CYGARC_8TCSR0,0x40,0x40),
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REGS_DEF(CYGARC_8TCR0,CYGARC_8TCSR0,0x80,0x80),
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REGS_DEF(CYGARC_8TCR1,CYGARC_8TCSR1,0xC0,0xC0),
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REGS_DEF(CYGARC_8TCR0,CYGARC_8TCSR0,0x20,0x20),
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REGS_DEF(CYGARC_8TCR2,CYGARC_8TCSR2,0x40,0x40),
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REGS_DEF(CYGARC_8TCR2,CYGARC_8TCSR2,0x80,0x80),
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REGS_DEF(CYGARC_8TCR3,CYGARC_8TCSR3,0xC0,0xC0),
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REGS_DEF(CYGARC_8TCR2,CYGARC_8TCSR2,0x20,0x20),
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REGS_DEF(CYGARC_DTCR0A,CYGARC_DTCR0A,0x08,0x80),
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REGS_DEF(CYGARC_DTCR0B,CYGARC_DTCR0B,0x08,0x80),
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REGS_DEF(CYGARC_DTCR1A,CYGARC_DTCR1A,0x08,0x80),
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REGS_DEF(CYGARC_DTCR1B,CYGARC_DTCR1B,0x08,0x80),
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REGS_DEF(NULL,NULL,0,0),
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REGS_DEF(NULL,NULL,0,0),
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REGS_DEF(NULL,NULL,0,0),
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REGS_DEF(NULL,NULL,0,0),
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REGS_DEF(CYGARC_SCR0,CYGARC_SSR0,0x40,0x30),
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REGS_DEF(CYGARC_SCR0,CYGARC_SSR0,0x40,0x40),
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REGS_DEF(CYGARC_SCR0,CYGARC_SSR0,0x80,0x80),
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REGS_DEF(CYGARC_SCR0,CYGARC_SSR0,0x04,0x04),
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REGS_DEF(CYGARC_SCR1,CYGARC_SSR1,0x40,0x30),
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REGS_DEF(CYGARC_SCR1,CYGARC_SSR1,0x40,0x40),
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REGS_DEF(CYGARC_SCR1,CYGARC_SSR1,0x80,0x80),
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REGS_DEF(CYGARC_SCR1,CYGARC_SSR1,0x04,0x04),
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REGS_DEF(CYGARC_SCR2,CYGARC_SSR2,0x40,0x30),
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REGS_DEF(CYGARC_SCR2,CYGARC_SSR2,0x40,0x40),
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REGS_DEF(CYGARC_SCR2,CYGARC_SSR2,0x80,0x80),
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REGS_DEF(CYGARC_SCR2,CYGARC_SSR2,0x04,0x04)
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};
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void
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hal_interrupt_mask(int vector)
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{
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CYG_BYTE ier;
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struct int_regs *regs=&interrupt_registers[vector-12];
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if (vector == CYGNUM_HAL_INTERRUPT_WDT) {
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HAL_READ_UINT8(CYGARC_TCSR,ier);
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ier &= ~0x20;
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HAL_WRITE_UINT16(CYGARC_TCSR,0xa500 | ier);
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} else {
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if ((vector > 12) && regs->ier) {
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HAL_READ_UINT8(regs->ier,ier);
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ier &= ~(regs->mask);
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HAL_WRITE_UINT8(regs->ier,ier);
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} else {
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CYG_FAIL("Unknown interrupt vector");
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}
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}
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}
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void
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hal_interrupt_unmask(int vector)
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{
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CYG_BYTE ier;
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struct int_regs *regs=&interrupt_registers[vector-12];
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if (vector == CYGNUM_HAL_INTERRUPT_WDT) {
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HAL_READ_UINT8(CYGARC_TCSR,ier);
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ier |= 0x20;
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HAL_WRITE_UINT16(CYGARC_TCSR,0xa500 | ier);
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} else {
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if ((vector > 12) && regs->ier) {
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HAL_READ_UINT8(regs->ier,ier);
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ier |= regs->mask;
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HAL_WRITE_UINT8(regs->ier,ier);
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} else {
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CYG_FAIL("Unknown interrupt vector");
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}
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}
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}
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void
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hal_interrupt_acknowledge(int vector)
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{
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CYG_BYTE isr;
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struct int_regs *regs=&interrupt_registers[vector-12];
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if (vector >= CYGNUM_HAL_INTERRUPT_DEND0A &&
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vector <= CYGNUM_HAL_INTERRUPT_DEND1B)
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return;
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if (vector == CYGNUM_HAL_INTERRUPT_WDT) {
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HAL_READ_UINT8(CYGARC_TCSR,isr);
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isr &= ~0x80;
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HAL_WRITE_UINT16(CYGARC_TCSR,0xa500 | isr);
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} else {
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if ((vector > 12) && regs->isr) {
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HAL_READ_UINT8(regs->isr,isr);
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isr &= ~(regs->status);
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HAL_WRITE_UINT8(regs->isr,isr);
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} else {
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CYG_FAIL("Unknown interrupt vector");
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}
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}
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}
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const short priority_table[]={
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7, 6, 5, 5, 4, 4,-1,-1,
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3, 3,-1, 3, 2, 2, 2, 2,
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1, 1, 1, 1, 0, 0, 0, 0,
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15,15,15,15,14,14,14,14,
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13,13,13,13,-1,-1,-1,-1,
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11,11,11,11,10,10,10,10,
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9,9,9,9
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};
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void
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hal_interrupt_set_level(int vector,int level)
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{
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CYG_BYTE *ipr;
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CYG_BYTE ipr_mask;
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int priority = priority_table[vector-12];
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ipr = (CYG_BYTE *)CYGARC_IPRA + ((priority & 0xf8) >> 3);
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if (priority>=0) {
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ipr_mask = 1 << (priority & 0x07);
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if (level == 0) {
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*ipr &= ~ipr_mask;
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} else {
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*ipr |= ipr_mask;
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}
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} else {
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CYG_FAIL("Unknown interrupt vector");
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}
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}
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void
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hal_interrupt_configure(int vector,int level,int up)
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{
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cyg_uint8 iscr,mask;
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if (vector >= CYGNUM_HAL_INTERRUPT_EXTERNAL_0 &&
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vector <= CYGNUM_HAL_INTERRUPT_EXTERNAL_7) {
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mask = 1 << (vector - CYGNUM_HAL_INTERRUPT_EXTERNAL_0);
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HAL_READ_UINT8(CYGARC_ISCR,iscr);
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if (level) {
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iscr &= ~mask;
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}
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if (up) {
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iscr |= mask;
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}
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CYG_ASSERT(!(up && level), "Cannot trigger on high level!");
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HAL_WRITE_UINT8(CYGARC_ISCR,iscr);
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} else {
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CYG_FAIL("Unhandled interrupt vector");
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}
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}
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/*------------------------------------------------------------------------*/
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/* End of var_misc.c */
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