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# ====================================================================

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#      hal_h8300_h8300h_sim.cdl

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#      H8/300H SIM HAL package configuration data

#

# ====================================================================

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## -------------------------------------------

## This file is part of eCos, the Embedded Configurable Operating System.

## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.

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# ====================================================================

######DESCRIPTIONBEGIN####

#

# Author(s):      jskov

# Original data:  bartv

# Contributors:

# Date:           1999-11-02

#

#####DESCRIPTIONEND####

#

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cdl_package CYGPKG_HAL_H8300_H8300H_SIM {

    display  "H8/300H simulator"

    parent        CYGPKG_HAL_H8300

    requires CYGPKG_HAL_H8300_H8300H

    implements CYGINT_HAL_VIRTUAL_VECTOR_SUPPORT

    implements    CYGINT_HAL_DEBUG_GDB_STUBS

    implements    CYGINT_HAL_DEBUG_GDB_STUBS_BREAK

    define_header hal_h8300_h8300h_sim.h

    include_dir   cyg/hal

    description   "

           The minimal simulator HAL package is provided for use when

           only a simple simulation of the processor architecture is

           desired, as opposed to detailed simulation of any specific

           board. In particular it is not possible to simulate any of

           the I/O devices, so device drivers cannot be used."

    compile       hal_diag.c plf_misc.c delay_us.S

    define_proc {

        puts $::cdl_system_header "#define CYGBLD_HAL_TARGET_H "

        puts $::cdl_system_header "#define CYGBLD_HAL_PLATFORM_H "

        puts $::cdl_header "#define CYG_HAL_H8300"

        puts $::cdl_header "#define CYGNUM_HAL_H8300_SCI_PORTS 1"

        puts $::cdl_header "#define CYGHWR_HAL_VECTOR_TABLE 0xfff000"

    }

    cdl_component CYG_HAL_STARTUP {

        display       "Startup type"

        flavor        data

        legal_values  {"RAM"}

        default_value {"RAM"}

        no_define

        define -file system.h CYG_HAL_STARTUP

        description   "

            Only supports RAM startup."

    }

    cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS {

        display      "Number of communication channels on the board"

        flavor       data

        calculated   1

    }

    cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL {

        display          "Debug serial port"

        flavor data

        legal_values     0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1

        default_value    0

        description      "

           The CQ/7708 board has only one serial port. This option

           chooses which port will be used to connect to a host

           running GDB."

    }

    # Real-time clock/counter specifics

    cdl_component CYGNUM_HAL_RTC_CONSTANTS {

        display       "Real-time clock constants."

        flavor        none

        cdl_option CYGNUM_HAL_RTC_NUMERATOR {

            display       "Real-time clock numerator"

            flavor        data

            calculated    1000000000

        }

        cdl_option CYGNUM_HAL_RTC_DENOMINATOR {

            display       "Real-time clock denominator"

            flavor        data

            calculated    100

        }

        cdl_option CYGNUM_HAL_H8300_RTC_PRESCALE {

            display       "Real-time clock base prescale"

            flavor        data

            calculated    8192

        }

        # Isn't a nice way to handle freq requirement!

        cdl_option CYGNUM_HAL_RTC_PERIOD {

            display       "Real-time clock period"

            flavor        data

            calculated    10

        }

    }

    cdl_option CYGHWR_HAL_H8300_CPG_INPUT {

        display "OSC/Clock Freqency"

        flavor  data

        default_value 8000000

    }

    cdl_component CYGBLD_GLOBAL_OPTIONS {

        display "Global build options"

        flavor  none

        parent  CYGPKG_NONE

        description   "

            Global build options including control over

            compiler flags, linker flags and choice of toolchain."

        cdl_option CYGBLD_GLOBAL_COMMAND_PREFIX {

            display "Global command prefix"

            flavor  data

            no_define

            default_value { "h8300-elf" }

            description "

                This option specifies the command prefix used when

                invoking the build tools."

        }

        cdl_option CYGBLD_GLOBAL_CFLAGS {

            display "Global compiler flags"

            flavor  data

            no_define

            default_value { "-Wall -Wpointer-arith -Wstrict-prototypes -Winline -Wundef -Woverloaded-virtual -g -O2 -mh -mint32 -fsigned-char -fdata-sections -fno-rtti -fno-exceptions -fvtable-gc -finit-priority" }

            description   "

                This option controls the global compiler flags which

                are used to compile all packages by

                default. Individual packages may define

                options which override these global flags."

        }

        cdl_option CYGBLD_GLOBAL_LDFLAGS {

            display "Global linker flags"

            flavor  data

            no_define

            default_value { "-g -nostdlib -Wl,--gc-sections -Wl,-static -mh" }

            description   "

                This option controls the global linker flags. Individual

                packages may define options which override these global flags."

        }

    }

    cdl_component CYGHWR_MEMORY_LAYOUT {

        display "Memory layout"

        flavor data

        no_define

        calculated { "h8300_h8300h_sim_ram" }

        cdl_option CYGHWR_MEMORY_LAYOUT_LDI {

            display "Memory layout linker script fragment"

            flavor data

            no_define

            define -file system.h CYGHWR_MEMORY_LAYOUT_LDI

            calculated { "" }

        }

        cdl_option CYGHWR_MEMORY_LAYOUT_H {

            display "Memory layout header file"

            flavor data

            no_define

            define -file system.h CYGHWR_MEMORY_LAYOUT_H

            calculated { "" }

        }

    }

}