OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [rtos/] [ecos-2.0/] [packages/] [hal/] [i386/] [arch/] [v2_0/] [src/] [context.S] - Blame information for rev 174

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 27 unneback
##=============================================================================
2
##
3
##      context.S
4
##
5
##      i386 context switch code
6
##
7
##=============================================================================
8
#####ECOSGPLCOPYRIGHTBEGIN####
9
## -------------------------------------------
10
## This file is part of eCos, the Embedded Configurable Operating System.
11
## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
12
##
13
## eCos is free software; you can redistribute it and/or modify it under
14
## the terms of the GNU General Public License as published by the Free
15
## Software Foundation; either version 2 or (at your option) any later version.
16
##
17
## eCos is distributed in the hope that it will be useful, but WITHOUT ANY
18
## WARRANTY; without even the implied warranty of MERCHANTABILITY or
19
## FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
20
## for more details.
21
##
22
## You should have received a copy of the GNU General Public License along
23
## with eCos; if not, write to the Free Software Foundation, Inc.,
24
## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
25
##
26
## As a special exception, if other files instantiate templates or use macros
27
## or inline functions from this file, or you compile this file and link it
28
## with other works to produce a work based on this file, this file does not
29
## by itself cause the resulting work to be covered by the GNU General Public
30
## License. However the source code for this file must still be made available
31
## in accordance with section (3) of the GNU General Public License.
32
##
33
## This exception does not invalidate any other reasons why a work based on
34
## this file might be covered by the GNU General Public License.
35
##
36
## Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
37
## at http://sources.redhat.com/ecos/ecos-license/
38
## -------------------------------------------
39
#####ECOSGPLCOPYRIGHTEND####
40
##=============================================================================
41
#######DESCRIPTIONBEGIN####
42
##
43
## Author(s):   jskov
44
## Contributors:jskov, pjo, nickg
45
## Date:        1999-01-20
46
## Purpose:     i386 context switch code
47
## Description: This file contains implementations of the thread context
48
##              switch routines. It also contains the longjmp() and setjmp()
49
##              routines.
50
##              Based on PowerPC context.S, using data from SYSV ABI4, i386
51
##              supplement (page 37-38)
52
##         http://www.sco.com/products/layered/develop/devspecs/abi386-4.pdf
53
##
54
######DESCRIPTIONEND####
55
##
56
##=============================================================================
57
 
58
#include 
59
 
60
#include 
61
 
62
#include 
63
 
64
#------------------------------------------------------------------------------
65
# function declaration macro
66
 
67
#define FUNC_START(name)                        \
68
        .globl name;                            \
69
name:
70
 
71
#------------------------------------------------------------------------------
72
# hal_thread_switch_context
73
# Switch thread contexts
74
# :     0(%esp) :     return address
75
# :     4(%esp) :     address of sp of next thread to execute
76
# :     8(%esp) :     address of sp save location of current thread
77
#
78
# %eax, %ecx, and %edx are ours to abuse.
79
 
80
FUNC_START(hal_thread_switch_context)
81
 
82
        # Pop the return address from the stack, but leave the
83
        # arguments there so that the caller can remove them
84
        # itself when we return.
85
 
86
        popl    %ecx            # pop return eip
87
        movl    0(%esp),%eax    # get next context ptr
88
        movl    4(%esp),%edx    # get this context ptr
89
 
90
        # Save context in the same format as an
91
        # exception
92
 
93
        pushfl                  # save eflags
94
        pushl   %cs             # save cs
95
        pushl   %ecx            # save eip
96
        pushl   $-1             # push fake vector
97
        pushal                  # push general registers
98
        hal_fpu_push_ctx        # push FPU state
99
 
100
        # Store the context ptr
101
        movl    %esp,(%edx)
102
 
103
hal_thread_switch_context_load:
104
 
105
        # The pointer to the next context is in EAX
106
 
107
        movl    (%eax),%esp     # Point ESP at new state
108
 
109
        # Merge the IF bit in the saved EFLAGS with the rest of the
110
        # bits currently in EFLAGS.
111
 
112
        movl    i386reg_eflags(%esp),%ebx # EBX = saved EFLAGS
113
        andl    $0x0200,%ebx    # isolate IF bit
114
        pushfl                  # push current flags
115
        popl    %ecx            # pop into ECX
116
        btrl    $9,%ecx         # clear IF flag in current EFLAGS
117
        orl     %ebx,%ecx       # Or in saved IF bit
118
        movl    %ecx,i386reg_eflags(%esp) # Restore to saved state for use by iret
119
 
120
        # Now we can load the state and enter next thread
121
 
122
        hal_fpu_pop_ctx         # Pop FPU state
123
        popal                   # unstack general registers
124
        add     $4,%esp         # skip vector number
125
 
126
        iret                    # And return
127
 
128
#------------------------------------------------------------------------------
129
# hal_thread_load_context
130
# Load thread context
131
# : 4(%esp) = address of sp of thread to execute
132
#
133
# %eax, %ecx, and %edx are ours to abuse.
134
 
135
FUNC_START(hal_thread_load_context)
136
 
137
        movl    4(%esp),%eax    # get new context ptr
138
 
139
        # Jump into hal_thread_switch_context at the right
140
        # point to load this context.
141
 
142
        jmp     hal_thread_switch_context_load
143
 
144
#------------------------------------------------------------------------------
145
# HAL longjmp, setjmp implementations
146
# hal_setjmp saves only to callee save registers ebp, ebx, esi, edi and
147
# and esp+pc into buffer supplied in 4(esp)
148
# Note: These definitions are repeated in hal_arch.h. If changes are required
149
# remember to update both sets.
150
 
151
#define CYGARC_JMP_BUF_SP        0
152
#define CYGARC_JMP_BUF_EBP       1
153
#define CYGARC_JMP_BUF_EBX       2
154
#define CYGARC_JMP_BUF_ESI       3
155
#define CYGARC_JMP_BUF_EDI       4
156
#define CYGARC_JMP_BUF_PC        5
157
 
158
#define CYGARC_JMP_BUF_SIZE      6
159
 
160
FUNC_START(hal_setjmp)
161
        # Get jmpbuf pointer
162
        movl    4(%esp),%eax
163
 
164
        # Save regular registers
165
        movl    %ebp,CYGARC_JMP_BUF_EBP*4(%eax)
166
        movl    %ebx,CYGARC_JMP_BUF_EBX*4(%eax)
167
        movl    %esi,CYGARC_JMP_BUF_ESI*4(%eax)
168
        movl    %edi,CYGARC_JMP_BUF_EDI*4(%eax)
169
 
170
        # Stack and PC
171
        movl    %esp,CYGARC_JMP_BUF_SP*4(%eax)
172
        movl    0(%esp),%edx
173
        movl    %edx,CYGARC_JMP_BUF_PC*4(%eax)
174
 
175
        # Return 0
176
        xor     %eax,%eax
177
        ret
178
 
179
 
180
# hal_longjmp loads state from 4(esp) and returns to PC stored in state
181
 
182
FUNC_START(hal_longjmp)
183
        # Get return value
184
        movl    8(%esp),%eax
185
 
186
        # Get jmpbuf pointer
187
        movl    4(%esp),%ecx
188
 
189
        # Restore regular registers
190
        movl    CYGARC_JMP_BUF_EBP*4(%ecx),%ebp
191
        movl    CYGARC_JMP_BUF_EBX*4(%ecx),%ebx
192
        movl    CYGARC_JMP_BUF_ESI*4(%ecx),%esi
193
        movl    CYGARC_JMP_BUF_EDI*4(%ecx),%edi
194
 
195
        # Restore stack pointer
196
        movl    CYGARC_JMP_BUF_SP*4(%ecx),%esp
197
 
198
        # Put return address on stack
199
        movl    CYGARC_JMP_BUF_PC*4(%ecx),%edx
200
        movl    %edx,0(%esp)
201
 
202
        ret
203
 
204
#-----------------------------------------------------------------------------
205
# End of context.S

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.