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[/] [openrisc/] [trunk/] [rtos/] [ecos-2.0/] [packages/] [hal/] [i386/] [pcmb/] [v2_0/] [src/] [pcmb_misc.c] - Blame information for rev 174

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//==========================================================================
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//
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//      pcmb_misc.c
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//
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//      HAL implementation miscellaneous functions
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//
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//==========================================================================
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//####ECOSGPLCOPYRIGHTBEGIN####
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// -------------------------------------------
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// This file is part of eCos, the Embedded Configurable Operating System.
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// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
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//
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// eCos is free software; you can redistribute it and/or modify it under
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// the terms of the GNU General Public License as published by the Free
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// Software Foundation; either version 2 or (at your option) any later version.
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//
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// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or
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// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
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// for more details.
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//
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// You should have received a copy of the GNU General Public License along
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// with eCos; if not, write to the Free Software Foundation, Inc.,
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// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
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//
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// As a special exception, if other files instantiate templates or use macros
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// or inline functions from this file, or you compile this file and link it
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// with other works to produce a work based on this file, this file does not
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// by itself cause the resulting work to be covered by the GNU General Public
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// License. However the source code for this file must still be made available
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// in accordance with section (3) of the GNU General Public License.
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//
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// This exception does not invalidate any other reasons why a work based on
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// this file might be covered by the GNU General Public License.
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//
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// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
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// at http://sources.redhat.com/ecos/ecos-license/
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// -------------------------------------------
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//####ECOSGPLCOPYRIGHTEND####
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//==========================================================================
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//#####DESCRIPTIONBEGIN####
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//
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// Author(s):    nickg
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// Contributors: nickg, jlarmour, pjo
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// Date:         1999-01-21
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// Purpose:      HAL miscellaneous functions
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// Description:  This file contains miscellaneous functions provided by the
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//               HAL.
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//
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//####DESCRIPTIONEND####
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//
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//========================================================================*/
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#include <pkgconf/hal.h>
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#include <pkgconf/hal_i386.h>
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#include <pkgconf/hal_i386_pcmb.h>
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#include <cyg/infra/cyg_type.h>         // Base types
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#include <cyg/infra/cyg_trac.h>         // tracing macros
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#include <cyg/infra/cyg_ass.h>          // assertion macros
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#include <cyg/hal/hal_intr.h>
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#include <cyg/hal/hal_io.h>
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#include <cyg/hal/hal_smp.h>
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/*------------------------------------------------------------------------*/
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// Array which stores the configured priority levels for the configured
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// interrupts.
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volatile CYG_BYTE hal_interrupt_level[CYGNUM_HAL_ISR_COUNT];
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/*------------------------------------------------------------------------*/
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// Static variables
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CYG_ADDRWORD cyg_hal_pcmb_memsize_base;
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CYG_ADDRWORD cyg_hal_pcmb_memsize_extended;
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/*------------------------------------------------------------------------*/
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// Initializer
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void hal_pcmb_init(void)
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{
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#ifdef CYGPKG_HAL_I386_PCMB_MEMSIZE_HARDCODE
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    cyg_hal_pcmb_memsize_base = CYGNUM_HAL_I386_PCMB_MEMSIZE_BASE;
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    cyg_hal_pcmb_memsize_extended = CYGNUM_HAL_I386_PCMB_MEMSIZE_EXTENDED;
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#endif
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#ifdef CYGPKG_HAL_I386_PCMB_MEMSIZE_BIOS
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    cyg_uint8 lo,hi;
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    HAL_READ_CMOS( 0x15, lo );
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    HAL_READ_CMOS( 0x16, hi );
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    cyg_hal_pcmb_memsize_base = ((hi<<8)+lo)*1024;
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#ifndef CYG_HAL_STARTUP_ROM
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    // If we started up under a BIOS, then it will have put
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    // the discovered extended memory size in CMOS bytes 30/31.
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    HAL_READ_CMOS( 0x30, lo );
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    HAL_READ_CMOS( 0x31, hi );
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#else
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    // 
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    HAL_READ_CMOS( 0x17, lo );
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    HAL_READ_CMOS( 0x18, hi );
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#endif
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    cyg_hal_pcmb_memsize_extended = ((hi<<8)+lo)*1024;
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#endif
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    // Disable NMI - this can be reenabled later, once a proper handler
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    // is registered and ready to handle events
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    HAL_WRITE_UINT8(0x70, 0x80);
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}
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/*------------------------------------------------------------------------*/
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cyg_uint8 *hal_i386_mem_real_region_top( cyg_uint8 *regionend )
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{
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    CYG_ASSERT( cyg_hal_pcmb_memsize_base > 0 , "No base RAM size set!");
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    CYG_ASSERT( cyg_hal_pcmb_memsize_extended > 0 , "No extended RAM size set!");
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    if( (CYG_ADDRESS)regionend <= 0x000A0000 )
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        regionend = (cyg_uint8 *)cyg_hal_pcmb_memsize_base;
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    else if( (CYG_ADDRESS)regionend >= 0x00100000 )
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        regionend = (cyg_uint8 *)cyg_hal_pcmb_memsize_extended+0x00100000;
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    return regionend;
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}
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/*------------------------------------------------------------------------*/
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// Clock initialization and access
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#ifdef CYGPKG_HAL_SMP_SUPPORT
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static HAL_SPINLOCK_TYPE pc_clock_lock;
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#else
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#define HAL_SPINLOCK_SPIN( lock )
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#define HAL_SPINLOCK_CLEAR( lock )
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#endif
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void hal_pc_clock_initialize(cyg_uint32 period)
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{
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    /* Select mode 2: rate generator.  Then we'll load LSB, and finally MSB. */
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    HAL_WRITE_UINT8( PC_PIT_CONTROL, 0x34 );
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    HAL_WRITE_UINT8( PC_PIT_CLOCK_0, period & 0xFF );
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    HAL_WRITE_UINT8( PC_PIT_CLOCK_0, period >> 8 );
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    HAL_SPINLOCK_CLEAR( pc_clock_lock );
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}
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void hal_pc_clock_read(cyg_uint32 * count)
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{
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    cyg_uint8 lo = 0,hi = 0;
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    cyg_uint32 curr = 0;
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    CYG_INTERRUPT_STATE interruptState ;
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    /* Hold off on interrupts for a bit. */
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    HAL_DISABLE_INTERRUPTS(interruptState) ;
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    HAL_SPINLOCK_SPIN( pc_clock_lock );
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    /* Latch counter 0. */
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    HAL_WRITE_UINT8(PC_PIT_CONTROL, 0x00);
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    /* Now get the value. */
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    HAL_READ_UINT8( PC_PIT_CLOCK_0, lo );
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    HAL_READ_UINT8( PC_PIT_CLOCK_0, hi );
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    curr = (hi<<8) | lo;
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    HAL_SPINLOCK_CLEAR( pc_clock_lock );
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    /* (Maybe) restore interrupts. */
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    HAL_RESTORE_INTERRUPTS(interruptState) ;
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    *count = CYGNUM_HAL_RTC_PERIOD - curr ;
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}
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/*------------------------------------------------------------------------*/
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void hal_idle_thread_action(cyg_uint32 loop_count)
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{
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#if 1 //ndef CYGPKG_HAL_SMP_SUPPORT
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    asm("hlt") ;
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#else    
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    CYG_WORD32 val;
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    CYG_WORD32 cpu = 0;
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#ifdef CYGPKG_HAL_SMP_SUPPORT    
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    cpu = HAL_SMP_CPU_THIS();
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    {
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        __externC HAL_SPINLOCK_TYPE cyg_hal_ioapic_lock;
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        HAL_SPINLOCK_SPIN( cyg_hal_ioapic_lock );
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        HAL_IOAPIC_READ( HAL_IOAPIC_REG_REDTBL+4, val );
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        PC_WRITE_SCREEN_32( PC_SCREEN_LINE(15)+10, val );
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        HAL_IOAPIC_READ( HAL_IOAPIC_REG_REDTBL+5, val );
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        PC_WRITE_SCREEN_32( PC_SCREEN_LINE(15), val );
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        HAL_SPINLOCK_CLEAR( cyg_hal_ioapic_lock );
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    }
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#endif
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    hal_pc_clock_read( &val);
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    PC_WRITE_SCREEN_32( PC_SCREEN_LINE(15)+20, val );
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#ifdef CYGPKG_HAL_SMP_SUPPORT    
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    PC_WRITE_SCREEN_8( PC_SCREEN_LINE(16+cpu), cpu);
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    HAL_APIC_READ( HAL_APIC_IRR, val );
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    PC_WRITE_SCREEN_32( PC_SCREEN_LINE(16+cpu)+10, val );
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    HAL_APIC_READ( HAL_APIC_IRR+1, val );
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    PC_WRITE_SCREEN_32( PC_SCREEN_LINE(16+cpu)+20, val );
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    HAL_APIC_READ( HAL_APIC_IRR+2, val );
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    PC_WRITE_SCREEN_32( PC_SCREEN_LINE(16+cpu)+30, val );
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#endif
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    HAL_QUERY_INTERRUPTS( val );
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    PC_WRITE_SCREEN_32( PC_SCREEN_LINE(16+cpu)+50, val );
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    PC_WRITE_SCREEN_32( PC_SCREEN_LINE(16+cpu)+60, loop_count );
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#endif
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}
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/*------------------------------------------------------------------------*/
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/* End of pcmb_misc.c                                                      */

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