OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [rtos/] [ecos-2.0/] [packages/] [hal/] [m68k/] [arch/] [v2_0/] [include/] [hal_intr.h] - Blame information for rev 565

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 27 unneback
#ifndef CYGONCE_HAL_HAL_INTR_H
2
#define CYGONCE_HAL_HAL_INTR_H
3
 
4
//==========================================================================
5
//
6
//      hal_intr.h
7
//
8
//      m68k Interrupt and clock support
9
//
10
//==========================================================================
11
//####ECOSGPLCOPYRIGHTBEGIN####
12
// -------------------------------------------
13
// This file is part of eCos, the Embedded Configurable Operating System.
14
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
15
//
16
// eCos is free software; you can redistribute it and/or modify it under
17
// the terms of the GNU General Public License as published by the Free
18
// Software Foundation; either version 2 or (at your option) any later version.
19
//
20
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
21
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
22
// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
23
// for more details.
24
//
25
// You should have received a copy of the GNU General Public License along
26
// with eCos; if not, write to the Free Software Foundation, Inc.,
27
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
28
//
29
// As a special exception, if other files instantiate templates or use macros
30
// or inline functions from this file, or you compile this file and link it
31
// with other works to produce a work based on this file, this file does not
32
// by itself cause the resulting work to be covered by the GNU General Public
33
// License. However the source code for this file must still be made available
34
// in accordance with section (3) of the GNU General Public License.
35
//
36
// This exception does not invalidate any other reasons why a work based on
37
// this file might be covered by the GNU General Public License.
38
//
39
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
40
// at http://sources.redhat.com/ecos/ecos-license/
41
// -------------------------------------------
42
//####ECOSGPLCOPYRIGHTEND####
43
//==========================================================================
44
 
45
#include <pkgconf/hal.h>
46
#include <cyg/infra/cyg_type.h>
47
#include <cyg/hal/hal_arch.h>
48
 
49
#include <cyg/hal/var_intr.h>
50
 
51
//--------------------------------------------------------------------------
52
// m68k exception vectors. These correspond to VSRs and are the values
53
// to use for HAL_VSR_GET/SET
54
#define CYGNUM_HAL_VECTOR_SSP               0
55
#define CYGNUM_HAL_VECTOR_RESET             1
56
#define CYGNUM_HAL_VECTOR_BUSERR            2
57
#define CYGNUM_HAL_VECTOR_ADDERR            3
58
#define CYGNUM_HAL_VECTOR_ILLINST           4
59
#define CYGNUM_HAL_VECTOR_ZERODIV           5
60
#define CYGNUM_HAL_VECTOR_CHKINST           6
61
#define CYGNUM_HAL_VECTOR_TRAPVINST         7
62
#define CYGNUM_HAL_VECTOR_PRIVVIOLATION     8
63
#define CYGNUM_HAL_VECTOR_TRACE             9
64
#define CYGNUM_HAL_VECTOR_L1010             10
65
#define CYGNUM_HAL_VECTOR_L1111             11
66
#define CYGNUM_HAL_VECTOR_UNINITINT         15
67
#define CYGNUM_HAL_VECTOR_SPURINT           24
68
#define CYGNUM_HAL_VECTOR_AUTOVEC1          25
69
#define CYGNUM_HAL_VECTOR_AUTOVEC2          26
70
#define CYGNUM_HAL_VECTOR_AUTOVEC3          27
71
#define CYGNUM_HAL_VECTOR_AUTOVEC4          28
72
#define CYGNUM_HAL_VECTOR_AUTOVEC5          29
73
#define CYGNUM_HAL_VECTOR_AUTOVEC6          30
74
#define CYGNUM_HAL_VECTOR_AUTOVEC7          31
75
#define CYGNUM_HAL_VECTOR_NMI               CYGNUM_HAL_VECTOR_AUTOVEC7
76
#define CYGNUM_HAL_VECTOR_TRAPFIRST         32
77
#define CYGNUM_HAL_VECTOR_NUMTRAPS          16
78
#define CYGNUM_HAL_VECTOR_TRAPLAST          (CYGNUM_HAL_VECTOR_TRAPFIRST+CYGNUM_HAL_VECTOR_NUMTRAPS-1)
79
#define CYGNUM_HAL_VECTOR_INTRFIRST         64
80
#define CYGNUM_HAL_VECTOR_NUMINTRS          192
81
#define CYGNUM_HAL_VECTOR_INTRLAST          (CYGNUM_HAL_VECTOR_INTRFIRST+CYGNUM_HAL_VECTOR_NUMINTRS-1)
82
 
83
#define CYGNUM_HAL_VSR_MIN                  CYGNUM_HAL_VECTOR_SSP
84
#define CYGNUM_HAL_VSR_MAX                  CYGNUM_HAL_VECTOR_INTRLAST
85
#define CYGNUM_HAL_VSR_COUNT                (CYGNUM_HAL_VSR_MAX+1)
86
 
87
//--------------------------------------------------------------------------
88
// Interrupt vectors.
89
 
90
#ifndef CYGNUM_HAL_ISR_MAX
91
#define CYGNUM_HAL_ISR_MIN                   0
92
#define CYGNUM_HAL_ISR_MAX                   255
93
#define CYGNUM_HAL_ISR_COUNT                 (7+CYGNUM_HAL_VECTOR_NUMINTRS)
94
#endif /* CYGNUM_HAL_ISR_MAX */
95
 
96
#ifndef CYGNUM_HAL_EXCEPTION_COUNT
97
#define CYGNUM_HAL_EXCEPTION_MIN             CYGNUM_HAL_VECTOR_BUSERR
98
#define CYGNUM_HAL_EXCEPTION_MAX             CYGNUM_HAL_VECTOR_SPURINT
99
#define CYGNUM_HAL_EXCEPTION_COUNT           ((CYGNUM_HAL_EXCEPTION_MAX-CYGNUM_HAL_EXCEPTION_MIN)+1)
100
#endif /* CYGNUM_HAL_EXCEPTION_COUNT */
101
 
102
//--------------------------------------------------------------------------
103
// Static data used by HAL
104
 
105
// ISR tables
106
externC volatile CYG_ADDRESS  cyg_hal_interrupt_handlers[CYGNUM_HAL_ISR_COUNT];
107
externC volatile CYG_ADDRWORD cyg_hal_interrupt_data[CYGNUM_HAL_ISR_COUNT];
108
externC volatile CYG_ADDRESS  cyg_hal_interrupt_objects[CYGNUM_HAL_ISR_COUNT];
109
 
110
// VSR table
111
externC volatile CYG_ADDRESS  cyg_hal_vsr_table[CYGNUM_HAL_VSR_COUNT];
112
 
113
//---------------------------------------------------------------------------
114
// Translate a vector number into an ISR table index.
115
 
116
#define HAL_TRANSLATE_VECTOR(_vector_,_index_)                              \
117
    CYG_MACRO_START                                                         \
118
    switch ((_vector_))                                                     \
119
    {                                                                       \
120
    case CYGNUM_HAL_VECTOR_AUTOVEC1 ... CYGNUM_HAL_VECTOR_AUTOVEC7:         \
121
        (_index_) = ((_vector_) - CYGNUM_HAL_VECTOR_AUTOVEC1);              \
122
        break;                                                              \
123
    case CYGNUM_HAL_VECTOR_INTRFIRST ... CYGNUM_HAL_VECTOR_INTRLAST:        \
124
        (_index_) = ((_vector_)                                             \
125
                     - CYGNUM_HAL_VECTOR_INTRFIRST                          \
126
                     + (CYGNUM_HAL_VECTOR_AUTOVEC7                          \
127
                        - CYGNUM_HAL_VECTOR_AUTOVEC1                        \
128
                        + 1));                                              \
129
        break;                                                              \
130
    default:                                                                \
131
        CYG_FAIL("Unknown Interrupt!!!");                                   \
132
        (_index_) = (typeof(_index_))-1;                                                     \
133
    }                                                                       \
134
    CYG_MACRO_END
135
 
136
//--------------------------------------------------------------------------
137
// Interrupt state storage
138
 
139
typedef cyg_uint16 CYG_INTERRUPT_STATE;
140
 
141
//---------------------------------------------------------------------------
142
// Interrupt and VSR attachment macros
143
 
144
externC cyg_uint32 hal_default_isr(CYG_ADDRWORD vector, CYG_ADDRWORD data);
145
externC void hal_default_exception_handler(CYG_WORD vector,
146
                                           HAL_SavedRegisters *regs);
147
 
148
#define HAL_INTERRUPT_IN_USE( _vector_, _state_)        \
149
    CYG_MACRO_START                                     \
150
    cyg_uint32 _index_;                                 \
151
    HAL_TRANSLATE_VECTOR ((_vector_), _index_);         \
152
                                                        \
153
    if (cyg_hal_interrupt_handlers[_index_]             \
154
        ==(CYG_ADDRESS)&hal_default_isr)                \
155
        (_state_) = 0;                                  \
156
    else                                                \
157
        (_state_) = 1;                                  \
158
    CYG_MACRO_END
159
 
160
#define HAL_INTERRUPT_ATTACH( _vector_, _isr_, _data_, _object_ )       \
161
    CYG_MACRO_START                                                     \
162
    cyg_uint32 _index_;                                                 \
163
    HAL_TRANSLATE_VECTOR((_vector_), _index_);                          \
164
                                                                        \
165
    if (cyg_hal_interrupt_handlers[_index_]                             \
166
        ==(CYG_ADDRESS)&hal_default_isr)                                \
167
    {                                                                   \
168
        cyg_hal_interrupt_handlers[_index_] = (CYG_ADDRESS)(_isr_);     \
169
        cyg_hal_interrupt_data[_index_] = (CYG_ADDRWORD)(_data_);       \
170
        cyg_hal_interrupt_objects[_index_] = (CYG_ADDRESS)(_object_);   \
171
    }                                                                   \
172
    CYG_MACRO_END
173
 
174
#define HAL_INTERRUPT_DETACH( _vector_, _isr_ ) \
175
CYG_MACRO_START \
176
    cyg_uint32 _index_; \
177
    HAL_INTERRUPT_MASK(_vector_); \
178
    HAL_TRANSLATE_VECTOR((_vector_), _index_); \
179
    if (cyg_hal_interrupt_handlers[_index_] \
180
        == (CYG_ADDRESS)(_isr_)) \
181
    { \
182
        cyg_hal_interrupt_handlers[_index_] = \
183
            (CYG_ADDRESS)&hal_default_isr; \
184
        cyg_hal_interrupt_data[_index_] = 0; \
185
        cyg_hal_interrupt_objects[_index_] = 0; \
186
    } \
187
CYG_MACRO_END
188
 
189
#define HAL_VSR_GET( _vector_, _pvsr_ )                         \
190
    *((CYG_ADDRESS *)(_pvsr_)) = cyg_hal_vsr_table[(_vector_)];
191
 
192
 
193
#define HAL_VSR_SET( _vector_, _vsr_, _poldvsr_ )                       \
194
    CYG_MACRO_START                                                     \
195
    if( (_poldvsr_) != NULL )                                           \
196
        *(CYG_ADDRESS *)(_poldvsr_) = cyg_hal_vsr_table[(_vector_)];    \
197
    cyg_hal_vsr_table[(_vector_)] = (CYG_ADDRESS)(_vsr_);               \
198
    CYG_MACRO_END
199
 
200
//--------------------------------------------------------------------------
201
// Interrupt control macros
202
 
203
//      The following interrupt control  macros are  the default  for the  68k
204
// architecture.   Some  architectures  will  override  these  definitions  by
205
// defining  them  in  their  var_intr.h  file.   Some  architectures  support
206
// instructions  like  andi.w  #xxxx,%sr   but  others   (Coldfire)  do   not.
207
// Architectures that support  these other  instructions will  want to  define
208
// their own macros.
209
 
210
#define HAL_M68K_SET_SR(__newsr__)                                          \
211
    CYG_MACRO_START                                                         \
212
    asm volatile ("move.w   %0,%%sr\n"                                      \
213
                  :                                                         \
214
                  : "g" ((CYG_INTERRUPT_STATE)(__newsr__)));                \
215
    CYG_MACRO_END
216
 
217
#ifndef HAL_ENABLE_INTERRUPTS
218
#define HAL_ENABLE_INTERRUPTS()                                             \
219
    CYG_MACRO_START                                                         \
220
    CYG_INTERRUPT_STATE _msk_;                                              \
221
    HAL_QUERY_INTERRUPTS(_msk_);                                            \
222
    HAL_M68K_SET_SR((_msk_ & (CYG_INTERRUPT_STATE)0xf8ff));                 \
223
    CYG_MACRO_END
224
#endif // HAL_ENABLE_INTERRUPTS
225
 
226
#ifndef HAL_DISABLE_INTERRUPTS
227
#define HAL_DISABLE_INTERRUPTS(_old_)                                       \
228
    CYG_MACRO_START                                                         \
229
    HAL_QUERY_INTERRUPTS(_old_);                                            \
230
    HAL_M68K_SET_SR((_old_ | (CYG_INTERRUPT_STATE)0x0700));                 \
231
    CYG_MACRO_END
232
#endif //HAL_DISABLE_INTERRUPTS
233
 
234
#define HAL_RESTORE_INTERRUPTS(_prev_)                                      \
235
    CYG_MACRO_START                                                         \
236
    CYG_INTERRUPT_STATE _msk_;                                              \
237
    HAL_QUERY_INTERRUPTS(_msk_);                                            \
238
    _msk_ &= (CYG_INTERRUPT_STATE)0xf8ff;                                   \
239
    _msk_ |= (((CYG_INTERRUPT_STATE)(_prev_))                               \
240
              & (CYG_INTERRUPT_STATE)0x0700);                               \
241
    asm volatile ("move.w   %0,%%sr\n"                                      \
242
                  :                                                         \
243
                  : "g" (_msk_));                                           \
244
    CYG_MACRO_END
245
 
246
// Use the extra assignment to avoid warnings.
247
// The compiler should optimize it out.
248
#define HAL_QUERY_INTERRUPTS(__oldmask__)                                   \
249
    CYG_MACRO_START                                                         \
250
    CYG_INTERRUPT_STATE _omsk_ = (CYG_INTERRUPT_STATE)(__oldmask__);        \
251
    asm volatile ("move.w   %%sr,%0\n"                                      \
252
                  : "=g" (_omsk_)                                           \
253
                  : );                                                      \
254
    (__oldmask__) = (typeof(__oldmask__))_omsk_;                            \
255
    CYG_MACRO_END
256
 
257
//---------------------------------------------------------------------------
258
#endif // ifndef CYGONCE_HAL_HAL_INTR_H
259
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.