OpenCores
URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [rtos/] [ecos-2.0/] [packages/] [hal/] [m68k/] [arch/] [v2_0/] [src/] [hal_misc.c] - Blame information for rev 27

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 27 unneback
//==========================================================================
2
//
3
//      hal_misc.c
4
//
5
//      HAL miscellaneous functions
6
//
7
//==========================================================================
8
//####ECOSGPLCOPYRIGHTBEGIN####
9
// -------------------------------------------
10
// This file is part of eCos, the Embedded Configurable Operating System.
11
// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
12
//
13
// eCos is free software; you can redistribute it and/or modify it under
14
// the terms of the GNU General Public License as published by the Free
15
// Software Foundation; either version 2 or (at your option) any later version.
16
//
17
// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
18
// WARRANTY; without even the implied warranty of MERCHANTABILITY or
19
// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
20
// for more details.
21
//
22
// You should have received a copy of the GNU General Public License along
23
// with eCos; if not, write to the Free Software Foundation, Inc.,
24
// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
25
//
26
// As a special exception, if other files instantiate templates or use macros
27
// or inline functions from this file, or you compile this file and link it
28
// with other works to produce a work based on this file, this file does not
29
// by itself cause the resulting work to be covered by the GNU General Public
30
// License. However the source code for this file must still be made available
31
// in accordance with section (3) of the GNU General Public License.
32
//
33
// This exception does not invalidate any other reasons why a work based on
34
// this file might be covered by the GNU General Public License.
35
//
36
// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
37
// at http://sources.redhat.com/ecos/ecos-license/
38
// -------------------------------------------
39
//####ECOSGPLCOPYRIGHTEND####
40
//==========================================================================
41
 
42
#include <pkgconf/hal.h>
43
 
44
#include <cyg/infra/cyg_type.h>
45
#include <cyg/infra/cyg_trac.h>         // tracing macros
46
#include <cyg/infra/cyg_ass.h>          // assertion macros
47
#include <cyg/infra/diag.h>             // diag_printf
48
 
49
#include <cyg/hal/hal_arch.h>           // HAL header
50
 
51
#include <cyg/hal/hal_intr.h>           // VSR/ISR defines
52
 
53
//--------------------------------------------------------------------------
54
// ISR tables
55
volatile CYG_ADDRESS  cyg_hal_interrupt_handlers[CYGNUM_HAL_ISR_COUNT];
56
volatile CYG_ADDRWORD cyg_hal_interrupt_data[CYGNUM_HAL_ISR_COUNT];
57
volatile CYG_ADDRESS  cyg_hal_interrupt_objects[CYGNUM_HAL_ISR_COUNT];
58
 
59
//--------------------------------------------------------------------------
60
// VSR table
61
 
62
//      The cyg_hal_vsr_table table is variant-specific.  Some processors must
63
// have the VSR table at specific locations.
64
 
65
/*****************************************************************************
66
hal_default_exception_handler -- First level C exception handler
67
 
68
     The assembly default VSR  handler calls  this routine  to handler  the
69
exception.  When this routine returns, the  state is restored to the  state
70
pointed to by regs.
71
 
72
     We declare this  routine as  weak so  that other  handlers can  easily
73
become the default exception handler.
74
 
75
INPUT:
76
 
77
     vector: The exception vector number.
78
 
79
     regs: A pointer to the saved state.
80
 
81
OUTPUT:
82
 
83
RETURN VALUE:
84
 
85
     None
86
 
87
*****************************************************************************/
88
 
89
externC void
90
hal_default_exception_handler(CYG_WORD vector, HAL_SavedRegisters *regs)
91
                                                    __attribute__ ((weak));
92
 
93
void hal_default_exception_handler(CYG_WORD vector, HAL_SavedRegisters *regs)
94
{
95
 
96
#ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
97
    externC void __handle_exception(void);
98
    externC HAL_SavedRegisters * _hal_registers;
99
 
100
    // Set the pointer to the registers of the current exception
101
    // context. At entry the GDB stub will expand the
102
    // HAL_SavedRegisters structure into a (bigger) register array.
103
    _hal_registers = regs;
104
 
105
    __handle_exception();
106
 
107
#elif defined(CYGFUN_HAL_COMMON_KERNEL_SUPPORT) && \
108
      defined(CYGPKG_HAL_EXCEPTIONS)
109
 
110
    // We should decode the vector and pass a more appropriate
111
    // value as the second argument. For now we simply pass a
112
    // pointer to the saved registers. We should also divert
113
    // breakpoint and other debug vectors into the debug stubs.
114
 
115
    cyg_hal_deliver_exception(vector, (CYG_ADDRWORD)regs);
116
 
117
#else
118
 
119
    CYG_FAIL("Exception!!!");
120
 
121
#endif
122
 
123
    return;
124
}
125
 
126
//---------------------------------------------------------------------------
127
// Default ISRs
128
 
129
externC cyg_uint32
130
hal_default_isr(CYG_ADDRWORD vector, CYG_ADDRWORD data)
131
{
132
    diag_printf("Spurious Interrupt: %d\n", vector);
133
 
134
//    CYG_FAIL("Spurious Interrupt!!!");
135
    return 0;
136
}
137
 
138
//---------------------------------------------------------------------------
139
// Idle thread action
140
 
141
void
142
hal_idle_thread_action( cyg_uint32 count )
143
{
144
}
145
 
146
//---------------------------------------------------------------------------
147
// Determine the index of the ls bit of the supplied mask.
148
 
149
cyg_uint32
150
hal_lsbit_index(cyg_uint32 mask)
151
{
152
    cyg_uint32 n = mask;
153
 
154
    static const signed char tab[64] =
155
    { -1, 0, 1, 12, 2, 6, 0, 13, 3, 0, 7, 0, 0, 0, 0, 14, 10,
156
      4, 0, 0, 8, 0, 0, 25, 0, 0, 0, 0, 0, 21, 27 , 15, 31, 11,
157
      5, 0, 0, 0, 0, 0, 9, 0, 0, 24, 0, 0 , 20, 26, 30, 0, 0, 0,
158
      0, 23, 0, 19, 29, 0, 22, 18, 28, 17, 16, 0
159
    };
160
 
161
    n &= ~(n-1UL);
162
    n = (n<<16)-n;
163
    n = (n<<6)+n;
164
    n = (n<<4)+n;
165
 
166
    return tab[n>>26];
167
}
168
 
169
//---------------------------------------------------------------------------
170
// Determine the index of the ms bit of the supplied mask.
171
 
172
cyg_uint32
173
hal_msbit_index(cyg_uint32 mask)
174
{
175
    cyg_uint32 x = mask;
176
    cyg_uint32 w;
177
 
178
    // Phase 1: make word with all ones from that one to the right.
179
    x |= x >> 16;
180
    x |= x >> 8;
181
    x |= x >> 4;
182
    x |= x >> 2;
183
    x |= x >> 1;
184
 
185
    // Phase 2: calculate number of "1" bits in the word.
186
    w = (x & 0x55555555) + ((x >> 1) & 0x55555555);
187
    w = (w & 0x33333333) + ((w >> 2) & 0x33333333);
188
    w = w + (w >> 4);
189
    w = (w & 0x000F000F) + ((w >> 8) & 0x000F000F);
190
    return (cyg_uint32)((w + (w >> 16)) & 0xFF);
191
 
192
}
193
 
194
//---------------------------------------------------------------------------
195
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.