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#ifndef MCF5272_SIM_H
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#define MCF5272_SIM_H
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//==========================================================================
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//####ECOSGPLCOPYRIGHTBEGIN####
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// -------------------------------------------
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// This file is part of eCos, the Embedded Configurable Operating System.
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// Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
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//
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// eCos is free software; you can redistribute it and/or modify it under
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// the terms of the GNU General Public License as published by the Free
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// Software Foundation; either version 2 or (at your option) any later version.
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//
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// eCos is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or
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// FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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// for more details.
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//
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// You should have received a copy of the GNU General Public License along
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// with eCos; if not, write to the Free Software Foundation, Inc.,
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// 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
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//
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// As a special exception, if other files instantiate templates or use macros
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// or inline functions from this file, or you compile this file and link it
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// with other works to produce a work based on this file, this file does not
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// by itself cause the resulting work to be covered by the GNU General Public
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// License. However the source code for this file must still be made available
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// in accordance with section (3) of the GNU General Public License.
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//
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// This exception does not invalidate any other reasons why a work based on
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// this file might be covered by the GNU General Public License.
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//
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// Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
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// at http://sources.redhat.com/ecos/ecos-license/
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// -------------------------------------------
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//####ECOSGPLCOPYRIGHTEND####
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//==========================================================================
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/*
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Defines for the mcf5272 System Integration Module (SIM)
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*/
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#include <pkgconf/hal.h>
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#include <cyg/infra/cyg_type.h>
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/* General configuration registers. */
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typedef struct mcf5272_sim_cfg_t
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{
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u32_t mbar; /* Module base address register */
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/* (MBAR), after initialization */
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u16_t scr; /* System configuration register */
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u16_t spr; /* System protection register */
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u32_t pmr; /* Power management register */
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u16_t res1;
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u16_t alpr; /* Active low power register */
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u32_t dir; /* Device identification register */
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u32_t res2[3];
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} __attribute__ ((aligned (4), packed)) mcf5272_sim_cfg_t;
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/* Interrupt controller registers. */
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typedef struct mcf5272_sim_int_t
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{
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u32_t icr[4]; /* Interrupt control register 1-4 */
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u32_t isr; /* Interrupt source register */
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u32_t pitr; /* Programmable interrupt */
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/* transition register */
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u32_t piwr; /* Programmable interrupt wakeup */
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/* register */
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u8_t res1[3];
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u8_t ipvr; /* Programmable interrupt vector */
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/* register */
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} __attribute__ ((aligned (4), packed)) mcf5272_sim_int_t;
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/* Chip Select Module */
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typedef struct mcf5272_sim_cs_t
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{
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u32_t csbr; /* CS base register. */
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u32_t csor; /* CS option register. */
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} __attribute__ ((aligned (4), packed)) mcf5272_sim_cs_t;
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/* General Purpose I/O Module */
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typedef struct mcf5272_sim_gpio_t
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{
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/* Use the following labels to initialize the bits in the data */
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/* direction registers. Setting the bit to zero indicates that this */
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/* pin is an input, one indicates an input. */
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#define MCF5272_GPIO_DDR_IN (0)
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#define MCF5272_GPIO_DDR_OUT (1)
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u32_t pacnt; /* Port A control register. */
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u16_t paddr; /* Port A data direction */
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/* register. */
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u16_t padat; /* Port A data register. */
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u32_t pbcnt; /* Port B control register. */
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/* Set these bits in the port B control register to enable the */
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/* Ethernet, UART0, and data transfer acknowledge pins. */
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#define MCF5272_GPIO_PBCNT_ETH_EN (0x55550000)
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#define MCF5272_GPIO_PBCNT_ETH_DE (0x00000000)
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#define MCF5272_GPIO_PBCNT_ETH_MSK (0xFFFF0000)
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#define MCF5272_GPIO_PBCNT_TA_EN (0x00000400)
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#define MCF5272_GPIO_PBCNT_TA_DE (0x00000000)
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#define MCF5272_GPIO_PBCNT_TA_MSK (0x00000C00)
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#define MCF5272_GPIO_PBCNT_URT0_EN (0x00000155)
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#define MCF5272_GPIO_PBCNT_URT0_DE (0x00000000)
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#define MCF5272_GPIO_PBCNT_URT0_MSK (0x000003FF)
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u16_t pbddr; /* Port B data direction */
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/* register. */
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u16_t pbdat; /* Port B data register. */
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u32_t res1;
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u16_t pcddr; /* Port C data direction */
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/* register. */
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u16_t pcdat; /* Port C data register. */
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u32_t pdcnt; /* Port D control register. */
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/* Set these bits in the port D control register to enable the UART1 */
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/* and interrupt 4 pins. */
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#define MCF5272_GPIO_PDCNT_INT4_EN (0x00000C00)
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#define MCF5272_GPIO_PDCNT_INT4_DE (0x00000000)
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#define MCF5272_GPIO_PDCNT_INT4_MSK (0x00000C00)
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#define MCF5272_GPIO_PDCNT_URT1_EN (0x000002AA)
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#define MCF5272_GPIO_PDCNT_URT1_DE (0x00000000)
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#define MCF5272_GPIO_PDCNT_URT1_MSK (0x000003FF)
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u16_t res2;
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u16_t res3;
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} __attribute__ ((aligned (4), packed)) mcf5272_sim_gpio_t;
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/* UART Module */
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typedef struct mcf5272_sim_uart_t
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{
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u8_t umr; /* UART mode register. */
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u8_t res1[3];
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#define MCF5272_UART_UMR_8BNP (0x13) /* Write this value to umr1 to */
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/* program the device for 8 bits */
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/* and no parity. */
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#define MCF5272_UART_UMR_1S (0x07) /* Write this value to umr2 to */
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/* program the device for 1 stop */
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/* bit. */
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u8_t usr_ucsr; /* UART status register (R) and */
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u8_t res2[3]; /* UART clock-select register (W). */
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#define MCF5272_UART_USR_RRDY (1<<0) /* Bit 0 of the device status */
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/* register is set when the receive */
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/* data register contains data. If */
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/* the data is not removed from the */
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/* holding register, additional */
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/* data will be placed in the FIFO */
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/* until the FIFO is overrun. */
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#define MCF5272_UART_USR_FFUL (1<<1) /* Bit 1 of the device status */
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/* register is set when the receive */
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/* data FIFO is full. If a */
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/* character is not removed before */
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/* the next character is received, */
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/* overrun will occur. */
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#define MCF5272_UART_USR_TXRDY (1<<2) /* Bit 2 of the device status */
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/* register is set when the */
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/* transmit data holding register */
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/* is empty. Note that this is */
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/* different than the FIFO being */
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/* empty as the FIFO may still */
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/* contain characters even if the */
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/* holding register is empty. */
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#define MCF5272_UART_USR_TXEMP (1<<3) /* Bit 3 of the device status */
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/* register is set when the */
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/* transmit data FIFO is empty. */
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#define MCF5272_UART_USR_OE (1<<4) /* Bit 4 of the device status */
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/* register is set when an overrun */
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/* error has occurred. */
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#define MCF5272_UART_USR_PE (1<<5) /* Bit 5 of the device status */
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/* register is set when a parity */
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/* error has occurred. */
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#define MCF5272_UART_USR_FE (1<<6) /* Bit 6 of the device status */
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/* register is set when a framing */
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/* error has occurred. */
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#define MCF5272_UART_USR_RB (1<<7) /* Bit 7 of the device status */
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/* register is set when a change in */
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/* break status has occurred on the */
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/* port. */
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#define MCF5272_UART_UCSR_CLKIN (0xDD) /* Writing this value to the ucsr */
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/* selects CLKIN/16 as the UART's */
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/* clock source. */
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u8_t ucr; /* UART command register (W). */
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u8_t res3[3];
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#define MCF5272_UART_UCR_RMR (0x01<<4) /* Write this value to ucr to */
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/* reset the mode register to umr1. */
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#define MCF5272_UART_UCR_RRX (0x02<<4) /* Write this value to ucr to */
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/* reset the receiver. */
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#define MCF5272_UART_UCR_RTX (0x03<<4) /* Write this value to ucr to */
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/* reset the transmitter. */
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#define MCF5272_UART_UCR_RES (0x04<<4) /* Write this value to ucr to */
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/* reset the error status. */
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#define MCF5272_UART_UCR_RBC (0x05<<4) /* Write this value to ucr to */
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/* reset the break change */
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/* interrupt. */
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#define MCF5272_UART_UCR_TXEN (1<<2) /* Write this value to ucr to */
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/* enable the transmitter. */
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#define MCF5272_UART_UCR_TXDE (1<<3) /* Write this value to ucr to */
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/* disable the transmitter. */
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#define MCF5272_UART_UCR_RXEN (1<<0) /* Write this value to ucr to */
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/* enable the receiver. */
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#define MCF5272_UART_UCR_RXDE (1<<1) /* Write this value to ucr to */
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/* disable the receiver. */
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/* Write this value to the ucr to */
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/* enablt the transmitter and */
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/* receiver. */
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#define MCF5272_UART_UCR_TXRXEN \
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(MCF5272_UART_UCR_TXEN | \
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MCF5272_UART_UCR_RXEN)
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u8_t urb_utb; /* UART receiver buffers (R) and */
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u8_t res4[3]; /* UART transmitter buffers (W). */
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u8_t uipcr_uacr; /* UART input port change */
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u8_t res5[3]; /* register (R) and UART auxiliary */
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/* control register (W). */
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u8_t uisr_uimr; /* UART interrupt status register */
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u8_t res6[3]; /* (R) and UART interrupt mask */
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/* register (W). */
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u8_t udu; /* UART divider upper register */
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u8_t res7[3]; /* (W). */
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u8_t udl; /* UART divider lower register */
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u8_t res8[3]; /* (W). */
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u8_t uabu; /* UART autobaud register MSB */
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u8_t res9[3]; /* (R). */
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u8_t uabl; /* UART autobaud register LSB */
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u8_t res10[3]; /* (R). */
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u8_t utf; /* UART transmitter FIFO */
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u8_t res11[3]; /* register. */
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#define MCF5272_UART_UTF_TXB (0x1F) /* Transmitter buffer data level. */
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/* Indicates the number of bytes */
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/* (0-24) currently stored in the */
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/* transmitter FIFO. */
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u8_t urf; /* UART receiver FIFO register. */
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u8_t res12[3];
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u8_t ufpd; /* UART Fractional Precision */
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u8_t res13[3]; /* Divider Control register. */
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u8_t uip; /* UART input port register (CTS) */
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u8_t res14[3]; /* (R). */
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u8_t uop1; /* UART output port bit set */
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u8_t res15[3]; /* command register (RTS) (W). */
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u8_t uop0; /* UART output port bit reset */
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u8_t res16[3]; /* command register (RTS) (W). */
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} __attribute__ ((aligned (4), packed)) mcf5272_sim_uart_t;
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/* Timer Module */
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typedef struct mcf5272_sim_timer_t
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{
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u16_t tmr; /* Timer Mode Register */
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u16_t res1;
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#define MCF5272_TIMER_TMR_PS 0xFF00 /* Prescaler. Programmed to */
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#define MCF5272_TIMER_TMR_PS_BIT 8 /* divide the clock input by values */
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/* from 1 to 256. The value */
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/* 0000_0000 divides the clock by */
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|
|
/* 1; the value 1111_1111 divides */
|
| 332 |
|
|
/* the clock by 256. */
|
| 333 |
|
|
|
| 334 |
|
|
#define MCF5272_TIMER_TMR_CE 0x00C0 /* Capture edge and enable */
|
| 335 |
|
|
#define MCF5272_TIMER_TMR_CE_BIT 6 /* interrupt. 00 Disable capture */
|
| 336 |
|
|
/* and interrupt on capture event */
|
| 337 |
|
|
/* 01 Capture on rising edge only */
|
| 338 |
|
|
/* and generate interrupt on */
|
| 339 |
|
|
/* capture event 10 Capture on */
|
| 340 |
|
|
/* falling edge only and generate */
|
| 341 |
|
|
/* interrupt on capture event 11 */
|
| 342 |
|
|
/* Capture on any edge and generate */
|
| 343 |
|
|
/* interrupt on capture event. */
|
| 344 |
|
|
|
| 345 |
|
|
#define MCF5272_TIMER_TMR_OM 0x0020 /* Output mode (TMR0 and TMR1 */
|
| 346 |
|
|
#define MCF5272_TIMER_TMR_OM_BIT 5 /* only. Reserved in TMR2 and */
|
| 347 |
|
|
/* TMR3). 0 Active-low pulse for */
|
| 348 |
|
|
/* one system clock cycle (15 nS at */
|
| 349 |
|
|
/* 66 MHz). 1 Toggle output; TOUTn */
|
| 350 |
|
|
/* is high at reset but is */
|
| 351 |
|
|
/* unavailable externally until the */
|
| 352 |
|
|
/* appropriate port control */
|
| 353 |
|
|
/* register is configured for this */
|
| 354 |
|
|
/* function. */
|
| 355 |
|
|
|
| 356 |
|
|
#define MCF5272_TIMER_TMR_ORI 0x0010 /* Output reference interrupt */
|
| 357 |
|
|
#define MCF5272_TIMER_TMR_ORI_BIT 4 /* enable. 0 Disable interrupt for */
|
| 358 |
|
|
/* reference reached (does not */
|
| 359 |
|
|
/* affect interrupt on capture */
|
| 360 |
|
|
/* function). 1 Enable interrupt */
|
| 361 |
|
|
/* upon reaching the reference */
|
| 362 |
|
|
/* value. If ORI is 1 when the */
|
| 363 |
|
|
/* TER[REF] is set, an immediate */
|
| 364 |
|
|
/* interrupt occurs. */
|
| 365 |
|
|
|
| 366 |
|
|
#define MCF5272_TIMER_TMR_FRR 0x0008 /* Free run/restart. 0 Free run. */
|
| 367 |
|
|
#define MCF5272_TIMER_TMR_FRR_BIT 3 /* Timer count continues to */
|
| 368 |
|
|
/* increment after the reference */
|
| 369 |
|
|
/* value is reached. 1 Restart. */
|
| 370 |
|
|
/* Timer count is reset immediately */
|
| 371 |
|
|
/* after the reference value is */
|
| 372 |
|
|
/* reached. */
|
| 373 |
|
|
|
| 374 |
|
|
#define MCF5272_TIMER_TMR_CLK 0x0006 /* Input clock source for the */
|
| 375 |
|
|
#define MCF5272_TIMER_TMR_CLK_BIT 1 /* timer. 00 Stop count. 01 */
|
| 376 |
|
|
/* Master system clock. 10 Master */
|
| 377 |
|
|
/* system clock divided by 16. */
|
| 378 |
|
|
/* TIN0 and TIN1 are external to */
|
| 379 |
|
|
/* the MCF5272 and are not */
|
| 380 |
|
|
/* synchronized to the system */
|
| 381 |
|
|
/* clock, so successive timeout */
|
| 382 |
|
|
/* lengths may vary slightly. 11 */
|
| 383 |
|
|
/* Corresponding TIN pin, TIN0 or */
|
| 384 |
|
|
/* TIN1 (falling edge), unused in */
|
| 385 |
|
|
/* TMR2 and TMR3. The minimum high */
|
| 386 |
|
|
/* and low periods for TIN as the */
|
| 387 |
|
|
/* clock source is 1 system clock, */
|
| 388 |
|
|
/* which gives a maximum TIN */
|
| 389 |
|
|
/* frequency of clock/2. */
|
| 390 |
|
|
|
| 391 |
|
|
#define MCF5272_TIMER_TMR_RST 0x0001 /* Reset timer. 0 A transition */
|
| 392 |
|
|
#define MCF5272_TIMER_TMR_RST_BIT 0 /* from 1 to 0 resets the timer. */
|
| 393 |
|
|
/* Other register values can be */
|
| 394 |
|
|
/* written. The */
|
| 395 |
|
|
/* counter/timer/prescaler are not */
|
| 396 |
|
|
/* clocked unless the timer is */
|
| 397 |
|
|
/* enabled. 1 Enable timer. */
|
| 398 |
|
|
|
| 399 |
|
|
u16_t trr; /* Timer Reference Register */
|
| 400 |
|
|
u16_t res2;
|
| 401 |
|
|
|
| 402 |
|
|
u16_t tcap; /* Timer Capture Register */
|
| 403 |
|
|
u16_t res3;
|
| 404 |
|
|
|
| 405 |
|
|
u16_t tcn; /* Timer Counter */
|
| 406 |
|
|
u16_t res4;
|
| 407 |
|
|
|
| 408 |
|
|
u16_t ter; /* Timer Event Register */
|
| 409 |
|
|
u16_t res5;
|
| 410 |
|
|
|
| 411 |
|
|
#define MCF5272_TIMER_TER_REF (0x0002) /* Output reference event. If */
|
| 412 |
|
|
#define MCF5272_TIMER_TER_REF_BIT (1) /* the bit is 0, the counter has */
|
| 413 |
|
|
/* not reached the TRR value; */
|
| 414 |
|
|
/* otherwise, the counter has */
|
| 415 |
|
|
/* reached the TRR value. Writing */
|
| 416 |
|
|
/* a 1 clears this bit. */
|
| 417 |
|
|
|
| 418 |
|
|
#define MCF5272_TIMER_TER_CAP (0x0001) /* Captuer event. If this bit is */
|
| 419 |
|
|
#define MCF5272_TIMER_TER_CAP_BIT (0) /* 0, the counter value has not */
|
| 420 |
|
|
/* been latched into the TCR; */
|
| 421 |
|
|
/* otherwise, the counter value is */
|
| 422 |
|
|
/* latched into the TCR. Writing a */
|
| 423 |
|
|
/* 1 clears this bit. */
|
| 424 |
|
|
|
| 425 |
|
|
u32_t res6[3];
|
| 426 |
|
|
|
| 427 |
|
|
} __attribute__ ((aligned (4), packed)) mcf5272_sim_timer_t;
|
| 428 |
|
|
|
| 429 |
|
|
/* Watchdog timer */
|
| 430 |
|
|
typedef struct mcf5272_sim_wdtmr_t
|
| 431 |
|
|
{
|
| 432 |
|
|
|
| 433 |
|
|
u16_t wrrr; /* Watchdog reset reference */
|
| 434 |
|
|
u16_t res1; /* register. */
|
| 435 |
|
|
|
| 436 |
|
|
u16_t wirr; /* Watchdog interrupt reference */
|
| 437 |
|
|
u16_t res2; /* register. */
|
| 438 |
|
|
|
| 439 |
|
|
u16_t wcr; /* Watchdog counter register. */
|
| 440 |
|
|
u16_t res3;
|
| 441 |
|
|
|
| 442 |
|
|
u16_t wer; /* Watchdog event register. */
|
| 443 |
|
|
u16_t res4;
|
| 444 |
|
|
|
| 445 |
|
|
u32_t res5[28];
|
| 446 |
|
|
|
| 447 |
|
|
} __attribute__ ((aligned (4), packed)) mcf5272_sim_wdtmr_t;
|
| 448 |
|
|
|
| 449 |
|
|
/* Ethernet Module */
|
| 450 |
|
|
typedef struct mcf5272_sim_enet_t
|
| 451 |
|
|
{
|
| 452 |
|
|
|
| 453 |
|
|
u8_t res1[0x40];
|
| 454 |
|
|
|
| 455 |
|
|
u32_t ecr; /* Ethernet control register */
|
| 456 |
|
|
|
| 457 |
|
|
u32_t eir; /* Interrupt event register */
|
| 458 |
|
|
|
| 459 |
|
|
u32_t eimr; /* Interrupt mask register */
|
| 460 |
|
|
|
| 461 |
|
|
u32_t ivsr; /* Interrupt vector status */
|
| 462 |
|
|
/* register */
|
| 463 |
|
|
|
| 464 |
|
|
u32_t rdar; /* Receive descriptor active */
|
| 465 |
|
|
/* register */
|
| 466 |
|
|
|
| 467 |
|
|
u32_t tdar; /* Transmit descriptor active */
|
| 468 |
|
|
/* register */
|
| 469 |
|
|
|
| 470 |
|
|
u8_t res2[0x0880-0x0858];
|
| 471 |
|
|
|
| 472 |
|
|
u32_t mmfr; /* MII management frame register */
|
| 473 |
|
|
|
| 474 |
|
|
u32_t mscr; /* MII speed control register */
|
| 475 |
|
|
|
| 476 |
|
|
u8_t res3[0x08cc-0x0888];
|
| 477 |
|
|
|
| 478 |
|
|
u32_t frbr; /* FIFO receive bound register */
|
| 479 |
|
|
|
| 480 |
|
|
u32_t frsr; /* FIFO receive start register */
|
| 481 |
|
|
|
| 482 |
|
|
u8_t res4[0x08e4-0x08d4];
|
| 483 |
|
|
|
| 484 |
|
|
u32_t tfwr; /* Transmit FIFO watermark */
|
| 485 |
|
|
|
| 486 |
|
|
u8_t res5[0x08ec-0x08e8];
|
| 487 |
|
|
|
| 488 |
|
|
u32_t tfsr; /* Transmit FIFO start register */
|
| 489 |
|
|
|
| 490 |
|
|
u8_t res6[0x0944-0x08f0];
|
| 491 |
|
|
|
| 492 |
|
|
u32_t rcr; /* Receive control register */
|
| 493 |
|
|
|
| 494 |
|
|
u32_t mflr; /* Maximum frame length register */
|
| 495 |
|
|
|
| 496 |
|
|
u8_t res7[0x0984-0x094c];
|
| 497 |
|
|
|
| 498 |
|
|
u32_t tcr; /* Transmit control register */
|
| 499 |
|
|
|
| 500 |
|
|
u8_t res8[0x0c00-0x0988];
|
| 501 |
|
|
|
| 502 |
|
|
u32_t malr; /* Lower 32-bits of MAC address */
|
| 503 |
|
|
|
| 504 |
|
|
u32_t maur; /* Upper 16-bits of MAC address */
|
| 505 |
|
|
|
| 506 |
|
|
u32_t htur; /* Upper 32-bits of hash table */
|
| 507 |
|
|
|
| 508 |
|
|
u32_t htlr; /* Lower 32-bits of hash table */
|
| 509 |
|
|
|
| 510 |
|
|
u32_t erdsr; /* Pointer to receive descriptor */
|
| 511 |
|
|
/* ring */
|
| 512 |
|
|
|
| 513 |
|
|
u32_t etdsr; /* Pointer to transmit descriptor */
|
| 514 |
|
|
/* ring */
|
| 515 |
|
|
|
| 516 |
|
|
u32_t emrbr; /* Maximum receive buffer size */
|
| 517 |
|
|
|
| 518 |
|
|
u8_t res9[0x0c40-0x0c1c];
|
| 519 |
|
|
|
| 520 |
|
|
u8_t efifo[448]; /* FIFO RAM space */
|
| 521 |
|
|
|
| 522 |
|
|
u8_t res10[0x1000-0x0e00];
|
| 523 |
|
|
|
| 524 |
|
|
} __attribute__ ((aligned (4), packed)) mcf5272_sim_enet_t;
|
| 525 |
|
|
|
| 526 |
|
|
/* System Integration Module (SIM) This structure defines each */
|
| 527 |
|
|
/* register's offset from the current value of the mbar register. */
|
| 528 |
|
|
typedef struct mcf5272_sim_t
|
| 529 |
|
|
{
|
| 530 |
|
|
|
| 531 |
|
|
mcf5272_sim_cfg_t cfg; /* 0x0000: General configuration */
|
| 532 |
|
|
/* registers. */
|
| 533 |
|
|
|
| 534 |
|
|
mcf5272_sim_int_t intc; /* 0x0020: Interrupt controller */
|
| 535 |
|
|
/* registers. */
|
| 536 |
|
|
|
| 537 |
|
|
mcf5272_sim_cs_t cs[8]; /* 0x0040: Chip Select Module */
|
| 538 |
|
|
|
| 539 |
|
|
mcf5272_sim_gpio_t gpio; /* 0x0080: General purpose I/O */
|
| 540 |
|
|
/* control registers */
|
| 541 |
|
|
|
| 542 |
|
|
u32_t qspi[8]; /* 0x00a0: Queued serial */
|
| 543 |
|
|
/* peripheral interface module. */
|
| 544 |
|
|
|
| 545 |
|
|
u32_t pwm[8]; /* 0x00c0: Pulse Width Modulation */
|
| 546 |
|
|
/* (PWM) Module */
|
| 547 |
|
|
|
| 548 |
|
|
u32_t dmac[8]; /* 0x00e0: DMA Controller */
|
| 549 |
|
|
|
| 550 |
|
|
mcf5272_sim_uart_t uart[2]; /* 0x0100: UART Modules */
|
| 551 |
|
|
|
| 552 |
|
|
u32_t sdramc[32]; /* 0x0180: SDRAM Controller */
|
| 553 |
|
|
|
| 554 |
|
|
mcf5272_sim_timer_t timer[4]; /* 0x0200: Timer Module */
|
| 555 |
|
|
|
| 556 |
|
|
mcf5272_sim_wdtmr_t wdtimer; /* 0x0280: Watchdog Timer Module */
|
| 557 |
|
|
|
| 558 |
|
|
u32_t plic[320]; /* 0x0300: Physical Layer */
|
| 559 |
|
|
/* Interface Controller */
|
| 560 |
|
|
|
| 561 |
|
|
mcf5272_sim_enet_t enet; /* 0x0800: Ethernet Module */
|
| 562 |
|
|
|
| 563 |
|
|
u32_t usb[512]; /* 0x1000: Universal Serial Bus */
|
| 564 |
|
|
|
| 565 |
|
|
} __attribute__ ((aligned (4), packed)) mcf5272_sim_t;
|
| 566 |
|
|
|
| 567 |
|
|
#endif /* MCF5272_SIM_H */
|
| 568 |
|
|
|
